1 /*
2 * Copyright (c) 2017 Lima Project
3 * Copyright (c) 2013 Connor Abbott
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 * THE SOFTWARE.
22 *
23 */
24
25 #ifndef LIMA_IR_PP_PPIR_H
26 #define LIMA_IR_PP_PPIR_H
27
28 #include "util/u_math.h"
29 #include "util/list.h"
30 #include "util/set.h"
31
32 #include "ir/lima_ir.h"
33
34 typedef enum {
35 ppir_op_mov,
36 ppir_op_abs,
37 ppir_op_neg,
38 ppir_op_sat,
39 ppir_op_add,
40
41 ppir_op_ddx,
42 ppir_op_ddy,
43
44 ppir_op_mul,
45 ppir_op_rcp,
46
47 ppir_op_sin_lut,
48 ppir_op_cos_lut,
49
50 ppir_op_sum3,
51 ppir_op_sum4,
52
53 ppir_op_normalize2,
54 ppir_op_normalize3,
55 ppir_op_normalize4,
56
57 ppir_op_select,
58
59 ppir_op_sin,
60 ppir_op_cos,
61 ppir_op_tan,
62 ppir_op_asin,
63 ppir_op_acos,
64
65 ppir_op_atan,
66 ppir_op_atan2,
67 ppir_op_atan_pt1,
68 ppir_op_atan2_pt1,
69 ppir_op_atan_pt2,
70
71 ppir_op_exp,
72 ppir_op_log,
73 ppir_op_exp2,
74 ppir_op_log2,
75 ppir_op_sqrt,
76 ppir_op_rsqrt,
77
78 ppir_op_sign,
79 ppir_op_floor,
80 ppir_op_ceil,
81 ppir_op_fract,
82 ppir_op_mod,
83 ppir_op_min,
84 ppir_op_max,
85 ppir_op_trunc,
86
87 ppir_op_and,
88 ppir_op_or,
89 ppir_op_xor,
90
91 ppir_op_lt,
92 ppir_op_gt,
93 ppir_op_le,
94 ppir_op_ge,
95 ppir_op_eq,
96 ppir_op_ne,
97 ppir_op_not,
98
99 ppir_op_load_uniform,
100 ppir_op_load_varying,
101 ppir_op_load_coords,
102 ppir_op_load_coords_reg,
103 ppir_op_load_fragcoord,
104 ppir_op_load_pointcoord,
105 ppir_op_load_frontface,
106 ppir_op_load_texture,
107 ppir_op_load_temp,
108
109 ppir_op_store_temp,
110
111 ppir_op_const,
112
113 ppir_op_discard,
114 ppir_op_branch,
115
116 ppir_op_undef,
117 ppir_op_dummy,
118
119 ppir_op_num,
120 } ppir_op;
121
122 typedef enum {
123 ppir_node_type_alu,
124 ppir_node_type_const,
125 ppir_node_type_load,
126 ppir_node_type_store,
127 ppir_node_type_load_texture,
128 ppir_node_type_discard,
129 ppir_node_type_branch,
130 } ppir_node_type;
131
132 typedef struct {
133 char *name;
134 ppir_node_type type;
135 int *slots;
136 } ppir_op_info;
137
138 extern const ppir_op_info ppir_op_infos[];
139
140 typedef enum {
141 ppir_dep_src,
142 ppir_dep_write_after_read,
143 ppir_dep_sequence,
144 } ppir_dep_type;
145
146 typedef struct {
147 void *pred, *succ;
148 ppir_dep_type type;
149 struct list_head pred_link;
150 struct list_head succ_link;
151 } ppir_dep;
152
153 typedef struct ppir_node {
154 struct list_head list;
155 struct list_head sched_list;
156 ppir_op op;
157 ppir_node_type type;
158 int index;
159 char name[16];
160 bool printed;
161 struct ppir_instr *instr;
162 int instr_pos;
163 struct ppir_block *block;
164 bool is_end;
165 bool succ_different_block;
166
167 /* for scheduler */
168 struct list_head succ_list;
169 struct list_head pred_list;
170 } ppir_node;
171
172 typedef enum {
173 ppir_pipeline_reg_const0,
174 ppir_pipeline_reg_const1,
175 ppir_pipeline_reg_sampler,
176 ppir_pipeline_reg_uniform,
177 ppir_pipeline_reg_vmul,
178 ppir_pipeline_reg_fmul,
179 ppir_pipeline_reg_discard, /* varying load */
180 } ppir_pipeline;
181
182 typedef struct ppir_reg {
183 struct list_head list;
184 int index;
185 int regalloc_index;
186 int num_components;
187
188 /* whether this reg has to start from the x component
189 * of a full physical reg, this is true for reg used
190 * in load/store instr which has no swizzle field */
191 bool is_head;
192 bool spilled;
193 bool undef;
194 } ppir_reg;
195
196 typedef enum {
197 ppir_target_ssa,
198 ppir_target_pipeline,
199 ppir_target_register,
200 } ppir_target;
201
202 typedef struct ppir_src {
203 ppir_target type;
204 ppir_node *node;
205
206 union {
207 ppir_reg *ssa;
208 ppir_reg *reg;
209 ppir_pipeline pipeline;
210 };
211
212 uint8_t swizzle[4];
213 bool absolute, negate;
214 } ppir_src;
215
216 typedef enum {
217 ppir_outmod_none,
218 ppir_outmod_clamp_fraction,
219 ppir_outmod_clamp_positive,
220 ppir_outmod_round,
221 } ppir_outmod;
222
223 typedef struct ppir_dest {
224 ppir_target type;
225
226 union {
227 ppir_reg ssa;
228 ppir_reg *reg;
229 ppir_pipeline pipeline;
230 };
231
232 ppir_outmod modifier;
233 unsigned write_mask : 4;
234 } ppir_dest;
235
236 typedef struct {
237 ppir_node node;
238 ppir_dest dest;
239 ppir_src src[3];
240 int num_src;
241 int shift : 3; /* Only used for ppir_op_mul */
242 } ppir_alu_node;
243
244 typedef struct ppir_const {
245 union fi value[4];
246 int num;
247 } ppir_const;
248
249 typedef struct {
250 ppir_node node;
251 ppir_const constant;
252 ppir_dest dest;
253 } ppir_const_node;
254
255 typedef struct {
256 ppir_node node;
257 int index;
258 int num_components;
259 ppir_dest dest;
260 ppir_src src;
261 int num_src;
262 } ppir_load_node;
263
264 typedef struct {
265 ppir_node node;
266 int index;
267 int num_components;
268 ppir_src src;
269 } ppir_store_node;
270
271 typedef struct {
272 ppir_node node;
273 ppir_dest dest;
274 ppir_src src[2];
275 int num_src;
276 int sampler;
277 int sampler_dim;
278 bool lod_bias_en;
279 bool explicit_lod;
280 } ppir_load_texture_node;
281
282 typedef struct {
283 ppir_node node;
284 } ppir_discard_node;
285
286 enum ppir_instr_slot {
287 PPIR_INSTR_SLOT_VARYING,
288 PPIR_INSTR_SLOT_TEXLD,
289 PPIR_INSTR_SLOT_UNIFORM,
290 PPIR_INSTR_SLOT_ALU_VEC_MUL,
291 PPIR_INSTR_SLOT_ALU_SCL_MUL,
292 PPIR_INSTR_SLOT_ALU_VEC_ADD,
293 PPIR_INSTR_SLOT_ALU_SCL_ADD,
294 PPIR_INSTR_SLOT_ALU_COMBINE,
295 PPIR_INSTR_SLOT_STORE_TEMP,
296 PPIR_INSTR_SLOT_BRANCH,
297 PPIR_INSTR_SLOT_NUM,
298 PPIR_INSTR_SLOT_END,
299 PPIR_INSTR_SLOT_ALU_START = PPIR_INSTR_SLOT_ALU_VEC_MUL,
300 PPIR_INSTR_SLOT_ALU_END = PPIR_INSTR_SLOT_ALU_COMBINE,
301 };
302
303 struct ppir_liveness {
304 ppir_reg *reg;
305 unsigned mask : 4;
306 };
307
308 typedef struct ppir_instr {
309 struct list_head list;
310 int index;
311 bool printed;
312 int seq; /* command sequence after schedule */
313
314 ppir_node *slots[PPIR_INSTR_SLOT_NUM];
315 ppir_const constant[2];
316 bool is_end;
317
318 /* for scheduler */
319 struct list_head succ_list;
320 struct list_head pred_list;
321 float reg_pressure;
322 int est; /* earliest start time */
323 int parent_index;
324 bool scheduled;
325 int offset;
326 int encode_size;
327
328 /* for liveness analysis */
329 struct ppir_liveness *live_in;
330 struct ppir_liveness *live_out;
331 /* live_internal is to mark registers only live within an
332 * instruction, without propagation */
333 struct ppir_liveness *live_internal;
334 struct set *live_in_set;
335 struct set *live_out_set;
336 struct set *live_internal_set;
337 } ppir_instr;
338
339 typedef struct ppir_block {
340 struct list_head list;
341 struct list_head node_list;
342 struct list_head instr_list;
343
344 struct ppir_block *successors[2];
345
346 struct ppir_compiler *comp;
347
348 /* for scheduler */
349 int sched_instr_index;
350 int sched_instr_base;
351 int index;
352
353 /* for liveness analysis */
354 struct ppir_liveness *live_in;
355 struct ppir_liveness *live_out;
356 struct set *live_in_set;
357 struct set *live_out_set;
358 } ppir_block;
359
360 typedef struct {
361 ppir_node node;
362 ppir_src src[2];
363 int num_src;
364 bool cond_gt;
365 bool cond_eq;
366 bool cond_lt;
367 bool negate;
368 ppir_block *target;
369 } ppir_branch_node;
370
371 struct ra_regs;
372 struct lima_fs_shader_state;
373
374 typedef struct ppir_compiler {
375 struct list_head block_list;
376 struct hash_table_u64 *blocks;
377 int cur_index;
378 int cur_instr_index;
379
380 struct list_head reg_list;
381
382 /* array for searching ssa/reg node */
383 ppir_node **var_nodes;
384 unsigned reg_base;
385
386 struct ra_regs *ra;
387 struct lima_fs_shader_state *prog;
388 bool uses_discard;
389
390 /* for scheduler */
391 int sched_instr_base;
392
393 /* for regalloc spilling debug */
394 int force_spilling;
395
396 /* shaderdb */
397 int num_loops;
398 int num_spills;
399 int num_fills;
400
401 ppir_block *discard_block;
402 ppir_block *current_block;
403 ppir_block *loop_break_block;
404 ppir_block *loop_cont_block;
405 } ppir_compiler;
406
407 void *ppir_node_create(ppir_block *block, ppir_op op, int index, unsigned mask);
408 void ppir_node_add_dep(ppir_node *succ, ppir_node *pred, ppir_dep_type type);
409 void ppir_node_remove_dep(ppir_dep *dep);
410 void ppir_node_delete(ppir_node *node);
411 void ppir_node_print_prog(ppir_compiler *comp);
412 void ppir_node_replace_child(ppir_node *parent, ppir_node *old_child, ppir_node *new_child);
413 void ppir_node_replace_all_succ(ppir_node *dst, ppir_node *src);
414 void ppir_node_replace_pred(ppir_dep *dep, ppir_node *new_pred);
415 ppir_dep *ppir_dep_for_pred(ppir_node *node, ppir_node *pred);
416 /* Assumes that node successors are in the same block */
417 ppir_node *ppir_node_insert_mov(ppir_node *node);
418
ppir_node_is_root(ppir_node * node)419 static inline bool ppir_node_is_root(ppir_node *node)
420 {
421 return list_is_empty(&node->succ_list);
422 }
423
ppir_node_is_leaf(ppir_node * node)424 static inline bool ppir_node_is_leaf(ppir_node *node)
425 {
426 return list_is_empty(&node->pred_list);
427 }
428
ppir_node_has_single_succ(ppir_node * node)429 static inline bool ppir_node_has_single_succ(ppir_node *node)
430 {
431 return list_is_singular(&node->succ_list)
432 && !node->succ_different_block;
433 }
434
435 bool ppir_node_has_single_src_succ(ppir_node *node);
436
ppir_node_first_succ(ppir_node * node)437 static inline ppir_node *ppir_node_first_succ(ppir_node *node)
438 {
439 return list_first_entry(&node->succ_list, ppir_dep, succ_link)->succ;
440 }
441
ppir_node_has_single_pred(ppir_node * node)442 static inline bool ppir_node_has_single_pred(ppir_node *node)
443 {
444 return list_is_singular(&node->pred_list);
445 }
446
ppir_node_first_pred(ppir_node * node)447 static inline ppir_node *ppir_node_first_pred(ppir_node *node)
448 {
449 return list_first_entry(&node->pred_list, ppir_dep, pred_link)->pred;
450 }
451
452 #define ppir_node_foreach_succ(node, dep) \
453 list_for_each_entry(ppir_dep, dep, &node->succ_list, succ_link)
454 #define ppir_node_foreach_succ_safe(node, dep) \
455 list_for_each_entry_safe(ppir_dep, dep, &node->succ_list, succ_link)
456 #define ppir_node_foreach_pred(node, dep) \
457 list_for_each_entry(ppir_dep, dep, &node->pred_list, pred_link)
458 #define ppir_node_foreach_pred_safe(node, dep) \
459 list_for_each_entry_safe(ppir_dep, dep, &node->pred_list, pred_link)
460
461 #define ppir_node_to_alu(node) ((ppir_alu_node *)(node))
462 #define ppir_node_to_const(node) ((ppir_const_node *)(node))
463 #define ppir_node_to_load(node) ((ppir_load_node *)(node))
464 #define ppir_node_to_store(node) ((ppir_store_node *)(node))
465 #define ppir_node_to_load_texture(node) ((ppir_load_texture_node *)(node))
466 #define ppir_node_to_discard(node) ((ppir_discard_node *)(node))
467 #define ppir_node_to_branch(node) ((ppir_branch_node *)(node))
468
ppir_node_get_dest(ppir_node * node)469 static inline ppir_dest *ppir_node_get_dest(ppir_node *node)
470 {
471 switch (node->type) {
472 case ppir_node_type_alu:
473 return &ppir_node_to_alu(node)->dest;
474 case ppir_node_type_load:
475 return &ppir_node_to_load(node)->dest;
476 case ppir_node_type_const:
477 return &ppir_node_to_const(node)->dest;
478 case ppir_node_type_load_texture:
479 return &ppir_node_to_load_texture(node)->dest;
480 default:
481 return NULL;
482 }
483 }
484
ppir_node_get_src_num(ppir_node * node)485 static inline int ppir_node_get_src_num(ppir_node *node)
486 {
487 switch (node->type) {
488 case ppir_node_type_alu:
489 return ppir_node_to_alu(node)->num_src;
490 case ppir_node_type_branch:
491 return ppir_node_to_branch(node)->num_src;
492 case ppir_node_type_load:
493 return ppir_node_to_load(node)->num_src;
494 case ppir_node_type_load_texture:
495 return ppir_node_to_load_texture(node)->num_src;
496 case ppir_node_type_store:
497 return 1;
498 default:
499 return 0;
500 }
501
502 return 0;
503 }
504
ppir_node_get_src(ppir_node * node,int idx)505 static inline ppir_src *ppir_node_get_src(ppir_node *node, int idx)
506 {
507 if (idx < 0 || idx >= ppir_node_get_src_num(node))
508 return NULL;
509
510 switch (node->type) {
511 case ppir_node_type_alu:
512 return &ppir_node_to_alu(node)->src[idx];
513 case ppir_node_type_branch:
514 return &ppir_node_to_branch(node)->src[idx];
515 case ppir_node_type_load_texture:
516 return &ppir_node_to_load_texture(node)->src[idx];
517 case ppir_node_type_load:
518 return &ppir_node_to_load(node)->src;
519 case ppir_node_type_store:
520 return &ppir_node_to_store(node)->src;
521 default:
522 break;
523 }
524
525 return NULL;
526 }
527
ppir_src_get_reg(ppir_src * src)528 static inline ppir_reg *ppir_src_get_reg(ppir_src *src)
529 {
530 switch (src->type) {
531 case ppir_target_ssa:
532 return src->ssa;
533 case ppir_target_register:
534 return src->reg;
535 default:
536 return NULL;
537 }
538 }
539
ppir_dest_get_reg(ppir_dest * dest)540 static inline ppir_reg *ppir_dest_get_reg(ppir_dest *dest)
541 {
542 switch (dest->type) {
543 case ppir_target_ssa:
544 return &dest->ssa;
545 case ppir_target_register:
546 return dest->reg;
547 default:
548 return NULL;
549 }
550 }
551
ppir_node_target_assign(ppir_src * src,ppir_node * node)552 static inline void ppir_node_target_assign(ppir_src *src, ppir_node *node)
553 {
554 ppir_dest *dest = ppir_node_get_dest(node);
555 src->type = dest->type;
556 switch (src->type) {
557 case ppir_target_ssa:
558 src->ssa = &dest->ssa;
559 src->node = node;
560 break;
561 case ppir_target_register:
562 src->reg = dest->reg;
563 /* Registers can be assigned from multiple nodes, so don't keep
564 * pointer to the node here
565 */
566 src->node = NULL;
567 break;
568 case ppir_target_pipeline:
569 src->pipeline = dest->pipeline;
570 src->node = node;
571 break;
572 }
573 }
574
ppir_node_target_equal(ppir_src * src,ppir_dest * dest)575 static inline bool ppir_node_target_equal(ppir_src *src, ppir_dest *dest)
576 {
577 if (src->type != dest->type ||
578 (src->type == ppir_target_ssa && src->ssa != &dest->ssa) ||
579 (src->type == ppir_target_register && src->reg != dest->reg) ||
580 (src->type == ppir_target_pipeline && src->pipeline != dest->pipeline))
581 return false;
582
583 return true;
584 }
585
ppir_target_get_src_reg_index(ppir_src * src)586 static inline int ppir_target_get_src_reg_index(ppir_src *src)
587 {
588 switch (src->type) {
589 case ppir_target_ssa:
590 if (src->ssa)
591 return src->ssa->index;
592 break;
593 case ppir_target_register:
594 if (src->reg)
595 return src->reg->index;
596 break;
597 case ppir_target_pipeline:
598 if (src->pipeline == ppir_pipeline_reg_discard)
599 return 15 * 4;
600 return (src->pipeline + 12) * 4;
601 }
602
603 return -1;
604 }
605
ppir_target_get_dest_reg_index(ppir_dest * dest)606 static inline int ppir_target_get_dest_reg_index(ppir_dest *dest)
607 {
608 switch (dest->type) {
609 case ppir_target_ssa:
610 return dest->ssa.index;
611 case ppir_target_register:
612 return dest->reg->index;
613 case ppir_target_pipeline:
614 if (dest->pipeline == ppir_pipeline_reg_discard)
615 return 15 * 4;
616 return (dest->pipeline + 12) * 4;
617 }
618
619 return -1;
620 }
621
ppir_src_get_mask(ppir_src * src)622 static inline int ppir_src_get_mask(ppir_src *src)
623 {
624 ppir_reg *reg = ppir_src_get_reg(src);
625 int mask = 0;
626
627 for (int i = 0; i < reg->num_components; i++)
628 mask |= (1 << src->swizzle[i]);
629
630 return mask;
631 }
632
ppir_target_is_scalar(ppir_dest * dest)633 static inline bool ppir_target_is_scalar(ppir_dest *dest)
634 {
635 switch (dest->type) {
636 case ppir_target_ssa:
637 return dest->ssa.num_components == 1;
638 case ppir_target_register:
639 /* only one bit in mask is set */
640 if ((dest->write_mask & 0x3) == 0x3 ||
641 (dest->write_mask & 0x5) == 0x5 ||
642 (dest->write_mask & 0x9) == 0x9 ||
643 (dest->write_mask & 0x6) == 0x6 ||
644 (dest->write_mask & 0xa) == 0xa ||
645 (dest->write_mask & 0xc) == 0xc)
646 return false;
647 else
648 return true;
649 case ppir_target_pipeline:
650 if (dest->pipeline == ppir_pipeline_reg_fmul)
651 return true;
652 else
653 return false;
654 default:
655 return false;
656 }
657 }
658
ppir_node_schedulable_slot(ppir_node * node,enum ppir_instr_slot slot)659 static inline bool ppir_node_schedulable_slot(ppir_node *node,
660 enum ppir_instr_slot slot)
661 {
662 int *slots = ppir_op_infos[node->op].slots;
663 for (int i = 0; slots[i] != PPIR_INSTR_SLOT_END; i++)
664 if (slots[i] == slot)
665 return true;
666
667 return false;
668 }
669
670 ppir_instr *ppir_instr_create(ppir_block *block);
671 bool ppir_instr_insert_node(ppir_instr *instr, ppir_node *node);
672 void ppir_instr_add_dep(ppir_instr *succ, ppir_instr *pred);
673 void ppir_instr_print_list(ppir_compiler *comp);
674 void ppir_instr_print_dep(ppir_compiler *comp);
675 void ppir_instr_insert_mul_node(ppir_node *add, ppir_node *mul);
676
677 #define ppir_instr_foreach_succ(instr, dep) \
678 list_for_each_entry(ppir_dep, dep, &instr->succ_list, succ_link)
679 #define ppir_instr_foreach_succ_safe(instr, dep) \
680 list_for_each_entry_safe(ppir_dep, dep, &instr->succ_list, succ_link)
681 #define ppir_instr_foreach_pred(instr, dep) \
682 list_for_each_entry(ppir_dep, dep, &instr->pred_list, pred_link)
683 #define ppir_instr_foreach_pred_safe(instr, dep) \
684 list_for_each_entry_safe(ppir_dep, dep, &instr->pred_list, pred_link)
685
ppir_instr_is_root(ppir_instr * instr)686 static inline bool ppir_instr_is_root(ppir_instr *instr)
687 {
688 return list_is_empty(&instr->succ_list);
689 }
690
ppir_instr_is_leaf(ppir_instr * instr)691 static inline bool ppir_instr_is_leaf(ppir_instr *instr)
692 {
693 return list_is_empty(&instr->pred_list);
694 }
695
696 bool ppir_lower_prog(ppir_compiler *comp);
697 bool ppir_node_to_instr(ppir_compiler *comp);
698 bool ppir_schedule_prog(ppir_compiler *comp);
699 bool ppir_regalloc_prog(ppir_compiler *comp);
700 bool ppir_codegen_prog(ppir_compiler *comp);
701 void ppir_liveness_analysis(ppir_compiler *comp);
702
703 #endif
704