1 /*
2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26 /**
27 * \file ir_to_mesa.cpp
28 *
29 * Translate GLSL IR to Mesa's gl_program representation.
30 */
31
32 #include <stdio.h>
33 #include "main/macros.h"
34 #include "main/mtypes.h"
35 #include "main/shaderapi.h"
36 #include "main/shaderobj.h"
37 #include "main/uniforms.h"
38 #include "main/glspirv.h"
39 #include "compiler/glsl/ast.h"
40 #include "compiler/glsl/ir.h"
41 #include "compiler/glsl/ir_expression_flattening.h"
42 #include "compiler/glsl/ir_visitor.h"
43 #include "compiler/glsl/ir_optimization.h"
44 #include "compiler/glsl/ir_uniform.h"
45 #include "compiler/glsl/glsl_parser_extras.h"
46 #include "compiler/glsl_types.h"
47 #include "compiler/glsl/linker.h"
48 #include "compiler/glsl/program.h"
49 #include "compiler/glsl/shader_cache.h"
50 #include "compiler/glsl/string_to_uint_map.h"
51 #include "program/prog_instruction.h"
52 #include "program/prog_optimize.h"
53 #include "program/prog_print.h"
54 #include "program/program.h"
55 #include "program/prog_parameter.h"
56
57
58 static int swizzle_for_size(int size);
59
60 namespace {
61
62 class src_reg;
63 class dst_reg;
64
65 /**
66 * This struct is a corresponding struct to Mesa prog_src_register, with
67 * wider fields.
68 */
69 class src_reg {
70 public:
src_reg(gl_register_file file,int index,const glsl_type * type)71 src_reg(gl_register_file file, int index, const glsl_type *type)
72 {
73 this->file = file;
74 this->index = index;
75 if (type && (type->is_scalar() || type->is_vector() || type->is_matrix()))
76 this->swizzle = swizzle_for_size(type->vector_elements);
77 else
78 this->swizzle = SWIZZLE_XYZW;
79 this->negate = 0;
80 this->reladdr = NULL;
81 }
82
src_reg()83 src_reg()
84 {
85 this->file = PROGRAM_UNDEFINED;
86 this->index = 0;
87 this->swizzle = 0;
88 this->negate = 0;
89 this->reladdr = NULL;
90 }
91
92 explicit src_reg(dst_reg reg);
93
94 gl_register_file file; /**< PROGRAM_* from Mesa */
95 int index; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
96 GLuint swizzle; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
97 int negate; /**< NEGATE_XYZW mask from mesa */
98 /** Register index should be offset by the integer in this reg. */
99 src_reg *reladdr;
100 };
101
102 class dst_reg {
103 public:
dst_reg(gl_register_file file,int writemask)104 dst_reg(gl_register_file file, int writemask)
105 {
106 this->file = file;
107 this->index = 0;
108 this->writemask = writemask;
109 this->reladdr = NULL;
110 }
111
dst_reg()112 dst_reg()
113 {
114 this->file = PROGRAM_UNDEFINED;
115 this->index = 0;
116 this->writemask = 0;
117 this->reladdr = NULL;
118 }
119
120 explicit dst_reg(src_reg reg);
121
122 gl_register_file file; /**< PROGRAM_* from Mesa */
123 int index; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
124 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
125 /** Register index should be offset by the integer in this reg. */
126 src_reg *reladdr;
127 };
128
129 } /* anonymous namespace */
130
src_reg(dst_reg reg)131 src_reg::src_reg(dst_reg reg)
132 {
133 this->file = reg.file;
134 this->index = reg.index;
135 this->swizzle = SWIZZLE_XYZW;
136 this->negate = 0;
137 this->reladdr = reg.reladdr;
138 }
139
dst_reg(src_reg reg)140 dst_reg::dst_reg(src_reg reg)
141 {
142 this->file = reg.file;
143 this->index = reg.index;
144 this->writemask = WRITEMASK_XYZW;
145 this->reladdr = reg.reladdr;
146 }
147
148 namespace {
149
150 class ir_to_mesa_instruction : public exec_node {
151 public:
152 DECLARE_RALLOC_CXX_OPERATORS(ir_to_mesa_instruction)
153
154 enum prog_opcode op;
155 dst_reg dst;
156 src_reg src[3];
157 /** Pointer to the ir source this tree came from for debugging */
158 ir_instruction *ir;
159 bool saturate;
160 int sampler; /**< sampler index */
161 int tex_target; /**< One of TEXTURE_*_INDEX */
162 GLboolean tex_shadow;
163 };
164
165 class variable_storage : public exec_node {
166 public:
variable_storage(ir_variable * var,gl_register_file file,int index)167 variable_storage(ir_variable *var, gl_register_file file, int index)
168 : file(file), index(index), var(var)
169 {
170 /* empty */
171 }
172
173 gl_register_file file;
174 int index;
175 ir_variable *var; /* variable that maps to this, if any */
176 };
177
178 class function_entry : public exec_node {
179 public:
180 ir_function_signature *sig;
181
182 /**
183 * identifier of this function signature used by the program.
184 *
185 * At the point that Mesa instructions for function calls are
186 * generated, we don't know the address of the first instruction of
187 * the function body. So we make the BranchTarget that is called a
188 * small integer and rewrite them during set_branchtargets().
189 */
190 int sig_id;
191
192 /**
193 * Pointer to first instruction of the function body.
194 *
195 * Set during function body emits after main() is processed.
196 */
197 ir_to_mesa_instruction *bgn_inst;
198
199 /**
200 * Index of the first instruction of the function body in actual
201 * Mesa IR.
202 *
203 * Set after convertion from ir_to_mesa_instruction to prog_instruction.
204 */
205 int inst;
206
207 /** Storage for the return value. */
208 src_reg return_reg;
209 };
210
211 class ir_to_mesa_visitor : public ir_visitor {
212 public:
213 ir_to_mesa_visitor();
214 ~ir_to_mesa_visitor();
215
216 function_entry *current_function;
217
218 struct gl_context *ctx;
219 struct gl_program *prog;
220 struct gl_shader_program *shader_program;
221 struct gl_shader_compiler_options *options;
222
223 int next_temp;
224
225 variable_storage *find_variable_storage(const ir_variable *var);
226
227 src_reg get_temp(const glsl_type *type);
228 void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
229
230 src_reg src_reg_for_float(float val);
231
232 /**
233 * \name Visit methods
234 *
235 * As typical for the visitor pattern, there must be one \c visit method for
236 * each concrete subclass of \c ir_instruction. Virtual base classes within
237 * the hierarchy should not have \c visit methods.
238 */
239 /*@{*/
240 virtual void visit(ir_variable *);
241 virtual void visit(ir_loop *);
242 virtual void visit(ir_loop_jump *);
243 virtual void visit(ir_function_signature *);
244 virtual void visit(ir_function *);
245 virtual void visit(ir_expression *);
246 virtual void visit(ir_swizzle *);
247 virtual void visit(ir_dereference_variable *);
248 virtual void visit(ir_dereference_array *);
249 virtual void visit(ir_dereference_record *);
250 virtual void visit(ir_assignment *);
251 virtual void visit(ir_constant *);
252 virtual void visit(ir_call *);
253 virtual void visit(ir_return *);
254 virtual void visit(ir_discard *);
255 virtual void visit(ir_demote *);
256 virtual void visit(ir_texture *);
257 virtual void visit(ir_if *);
258 virtual void visit(ir_emit_vertex *);
259 virtual void visit(ir_end_primitive *);
260 virtual void visit(ir_barrier *);
261 /*@}*/
262
263 src_reg result;
264
265 /** List of variable_storage */
266 exec_list variables;
267
268 /** List of function_entry */
269 exec_list function_signatures;
270 int next_signature_id;
271
272 /** List of ir_to_mesa_instruction */
273 exec_list instructions;
274
275 ir_to_mesa_instruction *emit(ir_instruction *ir, enum prog_opcode op);
276
277 ir_to_mesa_instruction *emit(ir_instruction *ir, enum prog_opcode op,
278 dst_reg dst, src_reg src0);
279
280 ir_to_mesa_instruction *emit(ir_instruction *ir, enum prog_opcode op,
281 dst_reg dst, src_reg src0, src_reg src1);
282
283 ir_to_mesa_instruction *emit(ir_instruction *ir, enum prog_opcode op,
284 dst_reg dst,
285 src_reg src0, src_reg src1, src_reg src2);
286
287 /**
288 * Emit the correct dot-product instruction for the type of arguments
289 */
290 ir_to_mesa_instruction * emit_dp(ir_instruction *ir,
291 dst_reg dst,
292 src_reg src0,
293 src_reg src1,
294 unsigned elements);
295
296 void emit_scalar(ir_instruction *ir, enum prog_opcode op,
297 dst_reg dst, src_reg src0);
298
299 void emit_scalar(ir_instruction *ir, enum prog_opcode op,
300 dst_reg dst, src_reg src0, src_reg src1);
301
302 bool try_emit_mad(ir_expression *ir,
303 int mul_operand);
304 bool try_emit_mad_for_and_not(ir_expression *ir,
305 int mul_operand);
306
307 void emit_swz(ir_expression *ir);
308
309 void emit_equality_comparison(ir_expression *ir, enum prog_opcode op,
310 dst_reg dst,
311 const src_reg &src0, const src_reg &src1);
312
emit_sne(ir_expression * ir,dst_reg dst,const src_reg & src0,const src_reg & src1)313 inline void emit_sne(ir_expression *ir, dst_reg dst,
314 const src_reg &src0, const src_reg &src1)
315 {
316 emit_equality_comparison(ir, OPCODE_SLT, dst, src0, src1);
317 }
318
emit_seq(ir_expression * ir,dst_reg dst,const src_reg & src0,const src_reg & src1)319 inline void emit_seq(ir_expression *ir, dst_reg dst,
320 const src_reg &src0, const src_reg &src1)
321 {
322 emit_equality_comparison(ir, OPCODE_SGE, dst, src0, src1);
323 }
324
325 bool process_move_condition(ir_rvalue *ir);
326
327 void copy_propagate(void);
328
329 void *mem_ctx;
330 };
331
332 } /* anonymous namespace */
333
334 static src_reg undef_src = src_reg(PROGRAM_UNDEFINED, 0, NULL);
335
336 static dst_reg undef_dst = dst_reg(PROGRAM_UNDEFINED, SWIZZLE_NOOP);
337
338 static dst_reg address_reg = dst_reg(PROGRAM_ADDRESS, WRITEMASK_X);
339
340 static int
swizzle_for_size(int size)341 swizzle_for_size(int size)
342 {
343 static const int size_swizzles[4] = {
344 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
345 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
346 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
347 MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
348 };
349
350 assert((size >= 1) && (size <= 4));
351 return size_swizzles[size - 1];
352 }
353
354 ir_to_mesa_instruction *
emit(ir_instruction * ir,enum prog_opcode op,dst_reg dst,src_reg src0,src_reg src1,src_reg src2)355 ir_to_mesa_visitor::emit(ir_instruction *ir, enum prog_opcode op,
356 dst_reg dst,
357 src_reg src0, src_reg src1, src_reg src2)
358 {
359 ir_to_mesa_instruction *inst = new(mem_ctx) ir_to_mesa_instruction();
360 int num_reladdr = 0;
361
362 /* If we have to do relative addressing, we want to load the ARL
363 * reg directly for one of the regs, and preload the other reladdr
364 * sources into temps.
365 */
366 num_reladdr += dst.reladdr != NULL;
367 num_reladdr += src0.reladdr != NULL;
368 num_reladdr += src1.reladdr != NULL;
369 num_reladdr += src2.reladdr != NULL;
370
371 reladdr_to_temp(ir, &src2, &num_reladdr);
372 reladdr_to_temp(ir, &src1, &num_reladdr);
373 reladdr_to_temp(ir, &src0, &num_reladdr);
374
375 if (dst.reladdr) {
376 emit(ir, OPCODE_ARL, address_reg, *dst.reladdr);
377 num_reladdr--;
378 }
379 assert(num_reladdr == 0);
380
381 inst->op = op;
382 inst->dst = dst;
383 inst->src[0] = src0;
384 inst->src[1] = src1;
385 inst->src[2] = src2;
386 inst->ir = ir;
387
388 this->instructions.push_tail(inst);
389
390 return inst;
391 }
392
393
394 ir_to_mesa_instruction *
emit(ir_instruction * ir,enum prog_opcode op,dst_reg dst,src_reg src0,src_reg src1)395 ir_to_mesa_visitor::emit(ir_instruction *ir, enum prog_opcode op,
396 dst_reg dst, src_reg src0, src_reg src1)
397 {
398 return emit(ir, op, dst, src0, src1, undef_src);
399 }
400
401 ir_to_mesa_instruction *
emit(ir_instruction * ir,enum prog_opcode op,dst_reg dst,src_reg src0)402 ir_to_mesa_visitor::emit(ir_instruction *ir, enum prog_opcode op,
403 dst_reg dst, src_reg src0)
404 {
405 assert(dst.writemask != 0);
406 return emit(ir, op, dst, src0, undef_src, undef_src);
407 }
408
409 ir_to_mesa_instruction *
emit(ir_instruction * ir,enum prog_opcode op)410 ir_to_mesa_visitor::emit(ir_instruction *ir, enum prog_opcode op)
411 {
412 return emit(ir, op, undef_dst, undef_src, undef_src, undef_src);
413 }
414
415 ir_to_mesa_instruction *
emit_dp(ir_instruction * ir,dst_reg dst,src_reg src0,src_reg src1,unsigned elements)416 ir_to_mesa_visitor::emit_dp(ir_instruction *ir,
417 dst_reg dst, src_reg src0, src_reg src1,
418 unsigned elements)
419 {
420 static const enum prog_opcode dot_opcodes[] = {
421 OPCODE_DP2, OPCODE_DP3, OPCODE_DP4
422 };
423
424 return emit(ir, dot_opcodes[elements - 2], dst, src0, src1);
425 }
426
427 /**
428 * Emits Mesa scalar opcodes to produce unique answers across channels.
429 *
430 * Some Mesa opcodes are scalar-only, like ARB_fp/vp. The src X
431 * channel determines the result across all channels. So to do a vec4
432 * of this operation, we want to emit a scalar per source channel used
433 * to produce dest channels.
434 */
435 void
emit_scalar(ir_instruction * ir,enum prog_opcode op,dst_reg dst,src_reg orig_src0,src_reg orig_src1)436 ir_to_mesa_visitor::emit_scalar(ir_instruction *ir, enum prog_opcode op,
437 dst_reg dst,
438 src_reg orig_src0, src_reg orig_src1)
439 {
440 int i, j;
441 int done_mask = ~dst.writemask;
442
443 /* Mesa RCP is a scalar operation splatting results to all channels,
444 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
445 * dst channels.
446 */
447 for (i = 0; i < 4; i++) {
448 GLuint this_mask = (1 << i);
449 ir_to_mesa_instruction *inst;
450 src_reg src0 = orig_src0;
451 src_reg src1 = orig_src1;
452
453 if (done_mask & this_mask)
454 continue;
455
456 GLuint src0_swiz = GET_SWZ(src0.swizzle, i);
457 GLuint src1_swiz = GET_SWZ(src1.swizzle, i);
458 for (j = i + 1; j < 4; j++) {
459 /* If there is another enabled component in the destination that is
460 * derived from the same inputs, generate its value on this pass as
461 * well.
462 */
463 if (!(done_mask & (1 << j)) &&
464 GET_SWZ(src0.swizzle, j) == src0_swiz &&
465 GET_SWZ(src1.swizzle, j) == src1_swiz) {
466 this_mask |= (1 << j);
467 }
468 }
469 src0.swizzle = MAKE_SWIZZLE4(src0_swiz, src0_swiz,
470 src0_swiz, src0_swiz);
471 src1.swizzle = MAKE_SWIZZLE4(src1_swiz, src1_swiz,
472 src1_swiz, src1_swiz);
473
474 inst = emit(ir, op, dst, src0, src1);
475 inst->dst.writemask = this_mask;
476 done_mask |= this_mask;
477 }
478 }
479
480 void
emit_scalar(ir_instruction * ir,enum prog_opcode op,dst_reg dst,src_reg src0)481 ir_to_mesa_visitor::emit_scalar(ir_instruction *ir, enum prog_opcode op,
482 dst_reg dst, src_reg src0)
483 {
484 src_reg undef = undef_src;
485
486 undef.swizzle = SWIZZLE_XXXX;
487
488 emit_scalar(ir, op, dst, src0, undef);
489 }
490
491 src_reg
src_reg_for_float(float val)492 ir_to_mesa_visitor::src_reg_for_float(float val)
493 {
494 src_reg src(PROGRAM_CONSTANT, -1, NULL);
495
496 src.index = _mesa_add_unnamed_constant(this->prog->Parameters,
497 (const gl_constant_value *)&val, 1, &src.swizzle);
498
499 return src;
500 }
501
502 static int
type_size(const struct glsl_type * type)503 type_size(const struct glsl_type *type)
504 {
505 return type->count_vec4_slots(false, false);
506 }
507
508 /**
509 * In the initial pass of codegen, we assign temporary numbers to
510 * intermediate results. (not SSA -- variable assignments will reuse
511 * storage). Actual register allocation for the Mesa VM occurs in a
512 * pass over the Mesa IR later.
513 */
514 src_reg
get_temp(const glsl_type * type)515 ir_to_mesa_visitor::get_temp(const glsl_type *type)
516 {
517 src_reg src;
518
519 src.file = PROGRAM_TEMPORARY;
520 src.index = next_temp;
521 src.reladdr = NULL;
522 next_temp += type_size(type);
523
524 if (type->is_array() || type->is_struct()) {
525 src.swizzle = SWIZZLE_NOOP;
526 } else {
527 src.swizzle = swizzle_for_size(type->vector_elements);
528 }
529 src.negate = 0;
530
531 return src;
532 }
533
534 variable_storage *
find_variable_storage(const ir_variable * var)535 ir_to_mesa_visitor::find_variable_storage(const ir_variable *var)
536 {
537 foreach_in_list(variable_storage, entry, &this->variables) {
538 if (entry->var == var)
539 return entry;
540 }
541
542 return NULL;
543 }
544
545 void
visit(ir_variable * ir)546 ir_to_mesa_visitor::visit(ir_variable *ir)
547 {
548 if (ir->data.mode == ir_var_uniform && strncmp(ir->name, "gl_", 3) == 0) {
549 unsigned int i;
550 const ir_state_slot *const slots = ir->get_state_slots();
551 assert(slots != NULL);
552
553 /* Check if this statevar's setup in the STATE file exactly
554 * matches how we'll want to reference it as a
555 * struct/array/whatever. If not, then we need to move it into
556 * temporary storage and hope that it'll get copy-propagated
557 * out.
558 */
559 for (i = 0; i < ir->get_num_state_slots(); i++) {
560 if (slots[i].swizzle != SWIZZLE_XYZW) {
561 break;
562 }
563 }
564
565 variable_storage *storage;
566 dst_reg dst;
567 if (i == ir->get_num_state_slots()) {
568 /* We'll set the index later. */
569 storage = new(mem_ctx) variable_storage(ir, PROGRAM_STATE_VAR, -1);
570 this->variables.push_tail(storage);
571
572 dst = undef_dst;
573 } else {
574 /* The variable_storage constructor allocates slots based on the size
575 * of the type. However, this had better match the number of state
576 * elements that we're going to copy into the new temporary.
577 */
578 assert((int) ir->get_num_state_slots() == type_size(ir->type));
579
580 storage = new(mem_ctx) variable_storage(ir, PROGRAM_TEMPORARY,
581 this->next_temp);
582 this->variables.push_tail(storage);
583 this->next_temp += type_size(ir->type);
584
585 dst = dst_reg(src_reg(PROGRAM_TEMPORARY, storage->index, NULL));
586 }
587
588
589 for (unsigned int i = 0; i < ir->get_num_state_slots(); i++) {
590 int index = _mesa_add_state_reference(this->prog->Parameters,
591 slots[i].tokens);
592
593 if (storage->file == PROGRAM_STATE_VAR) {
594 if (storage->index == -1) {
595 storage->index = index;
596 } else {
597 assert(index == storage->index + (int)i);
598 }
599 } else {
600 src_reg src(PROGRAM_STATE_VAR, index, NULL);
601 src.swizzle = slots[i].swizzle;
602 emit(ir, OPCODE_MOV, dst, src);
603 /* even a float takes up a whole vec4 reg in a struct/array. */
604 dst.index++;
605 }
606 }
607
608 if (storage->file == PROGRAM_TEMPORARY &&
609 dst.index != storage->index + (int) ir->get_num_state_slots()) {
610 linker_error(this->shader_program,
611 "failed to load builtin uniform `%s' "
612 "(%d/%d regs loaded)\n",
613 ir->name, dst.index - storage->index,
614 type_size(ir->type));
615 }
616 }
617 }
618
619 void
visit(ir_loop * ir)620 ir_to_mesa_visitor::visit(ir_loop *ir)
621 {
622 emit(NULL, OPCODE_BGNLOOP);
623
624 visit_exec_list(&ir->body_instructions, this);
625
626 emit(NULL, OPCODE_ENDLOOP);
627 }
628
629 void
visit(ir_loop_jump * ir)630 ir_to_mesa_visitor::visit(ir_loop_jump *ir)
631 {
632 switch (ir->mode) {
633 case ir_loop_jump::jump_break:
634 emit(NULL, OPCODE_BRK);
635 break;
636 case ir_loop_jump::jump_continue:
637 emit(NULL, OPCODE_CONT);
638 break;
639 }
640 }
641
642
643 void
visit(ir_function_signature * ir)644 ir_to_mesa_visitor::visit(ir_function_signature *ir)
645 {
646 assert(0);
647 (void)ir;
648 }
649
650 void
visit(ir_function * ir)651 ir_to_mesa_visitor::visit(ir_function *ir)
652 {
653 /* Ignore function bodies other than main() -- we shouldn't see calls to
654 * them since they should all be inlined before we get to ir_to_mesa.
655 */
656 if (strcmp(ir->name, "main") == 0) {
657 const ir_function_signature *sig;
658 exec_list empty;
659
660 sig = ir->matching_signature(NULL, &empty, false);
661
662 assert(sig);
663
664 foreach_in_list(ir_instruction, ir, &sig->body) {
665 ir->accept(this);
666 }
667 }
668 }
669
670 bool
try_emit_mad(ir_expression * ir,int mul_operand)671 ir_to_mesa_visitor::try_emit_mad(ir_expression *ir, int mul_operand)
672 {
673 int nonmul_operand = 1 - mul_operand;
674 src_reg a, b, c;
675
676 ir_expression *expr = ir->operands[mul_operand]->as_expression();
677 if (!expr || expr->operation != ir_binop_mul)
678 return false;
679
680 expr->operands[0]->accept(this);
681 a = this->result;
682 expr->operands[1]->accept(this);
683 b = this->result;
684 ir->operands[nonmul_operand]->accept(this);
685 c = this->result;
686
687 this->result = get_temp(ir->type);
688 emit(ir, OPCODE_MAD, dst_reg(this->result), a, b, c);
689
690 return true;
691 }
692
693 /**
694 * Emit OPCODE_MAD(a, -b, a) instead of AND(a, NOT(b))
695 *
696 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
697 * implemented using multiplication, and logical-or is implemented using
698 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
699 * As result, the logical expression (a & !b) can be rewritten as:
700 *
701 * - a * !b
702 * - a * (1 - b)
703 * - (a * 1) - (a * b)
704 * - a + -(a * b)
705 * - a + (a * -b)
706 *
707 * This final expression can be implemented as a single MAD(a, -b, a)
708 * instruction.
709 */
710 bool
try_emit_mad_for_and_not(ir_expression * ir,int try_operand)711 ir_to_mesa_visitor::try_emit_mad_for_and_not(ir_expression *ir, int try_operand)
712 {
713 const int other_operand = 1 - try_operand;
714 src_reg a, b;
715
716 ir_expression *expr = ir->operands[try_operand]->as_expression();
717 if (!expr || expr->operation != ir_unop_logic_not)
718 return false;
719
720 ir->operands[other_operand]->accept(this);
721 a = this->result;
722 expr->operands[0]->accept(this);
723 b = this->result;
724
725 b.negate = ~b.negate;
726
727 this->result = get_temp(ir->type);
728 emit(ir, OPCODE_MAD, dst_reg(this->result), a, b, a);
729
730 return true;
731 }
732
733 void
reladdr_to_temp(ir_instruction * ir,src_reg * reg,int * num_reladdr)734 ir_to_mesa_visitor::reladdr_to_temp(ir_instruction *ir,
735 src_reg *reg, int *num_reladdr)
736 {
737 if (!reg->reladdr)
738 return;
739
740 emit(ir, OPCODE_ARL, address_reg, *reg->reladdr);
741
742 if (*num_reladdr != 1) {
743 src_reg temp = get_temp(glsl_type::vec4_type);
744
745 emit(ir, OPCODE_MOV, dst_reg(temp), *reg);
746 *reg = temp;
747 }
748
749 (*num_reladdr)--;
750 }
751
752 void
emit_swz(ir_expression * ir)753 ir_to_mesa_visitor::emit_swz(ir_expression *ir)
754 {
755 /* Assume that the vector operator is in a form compatible with OPCODE_SWZ.
756 * This means that each of the operands is either an immediate value of -1,
757 * 0, or 1, or is a component from one source register (possibly with
758 * negation).
759 */
760 uint8_t components[4] = { 0 };
761 bool negate[4] = { false };
762 ir_variable *var = NULL;
763
764 for (unsigned i = 0; i < ir->type->vector_elements; i++) {
765 ir_rvalue *op = ir->operands[i];
766
767 assert(op->type->is_scalar());
768
769 while (op != NULL) {
770 switch (op->ir_type) {
771 case ir_type_constant: {
772
773 assert(op->type->is_scalar());
774
775 const ir_constant *const c = op->as_constant();
776 if (c->is_one()) {
777 components[i] = SWIZZLE_ONE;
778 } else if (c->is_zero()) {
779 components[i] = SWIZZLE_ZERO;
780 } else if (c->is_negative_one()) {
781 components[i] = SWIZZLE_ONE;
782 negate[i] = true;
783 } else {
784 assert(!"SWZ constant must be 0.0 or 1.0.");
785 }
786
787 op = NULL;
788 break;
789 }
790
791 case ir_type_dereference_variable: {
792 ir_dereference_variable *const deref =
793 (ir_dereference_variable *) op;
794
795 assert((var == NULL) || (deref->var == var));
796 components[i] = SWIZZLE_X;
797 var = deref->var;
798 op = NULL;
799 break;
800 }
801
802 case ir_type_expression: {
803 ir_expression *const expr = (ir_expression *) op;
804
805 assert(expr->operation == ir_unop_neg);
806 negate[i] = true;
807
808 op = expr->operands[0];
809 break;
810 }
811
812 case ir_type_swizzle: {
813 ir_swizzle *const swiz = (ir_swizzle *) op;
814
815 components[i] = swiz->mask.x;
816 op = swiz->val;
817 break;
818 }
819
820 default:
821 assert(!"Should not get here.");
822 return;
823 }
824 }
825 }
826
827 assert(var != NULL);
828
829 ir_dereference_variable *const deref =
830 new(mem_ctx) ir_dereference_variable(var);
831
832 this->result.file = PROGRAM_UNDEFINED;
833 deref->accept(this);
834 if (this->result.file == PROGRAM_UNDEFINED) {
835 printf("Failed to get tree for expression operand:\n");
836 deref->print();
837 printf("\n");
838 exit(1);
839 }
840
841 src_reg src;
842
843 src = this->result;
844 src.swizzle = MAKE_SWIZZLE4(components[0],
845 components[1],
846 components[2],
847 components[3]);
848 src.negate = ((unsigned(negate[0]) << 0)
849 | (unsigned(negate[1]) << 1)
850 | (unsigned(negate[2]) << 2)
851 | (unsigned(negate[3]) << 3));
852
853 /* Storage for our result. Ideally for an assignment we'd be using the
854 * actual storage for the result here, instead.
855 */
856 const src_reg result_src = get_temp(ir->type);
857 dst_reg result_dst = dst_reg(result_src);
858
859 /* Limit writes to the channels that will be used by result_src later.
860 * This does limit this temp's use as a temporary for multi-instruction
861 * sequences.
862 */
863 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
864
865 emit(ir, OPCODE_SWZ, result_dst, src);
866 this->result = result_src;
867 }
868
869 void
emit_equality_comparison(ir_expression * ir,enum prog_opcode op,dst_reg dst,const src_reg & src0,const src_reg & src1)870 ir_to_mesa_visitor::emit_equality_comparison(ir_expression *ir,
871 enum prog_opcode op,
872 dst_reg dst,
873 const src_reg &src0,
874 const src_reg &src1)
875 {
876 src_reg difference;
877 src_reg abs_difference = get_temp(glsl_type::vec4_type);
878 const src_reg zero = src_reg_for_float(0.0);
879
880 /* x == y is equivalent to -abs(x-y) >= 0. Since all of the code that
881 * consumes the generated IR is pretty dumb, take special care when one
882 * of the operands is zero.
883 *
884 * Similarly, x != y is equivalent to -abs(x-y) < 0.
885 */
886 if (src0.file == zero.file &&
887 src0.index == zero.index &&
888 src0.swizzle == zero.swizzle) {
889 difference = src1;
890 } else if (src1.file == zero.file &&
891 src1.index == zero.index &&
892 src1.swizzle == zero.swizzle) {
893 difference = src0;
894 } else {
895 difference = get_temp(glsl_type::vec4_type);
896
897 src_reg tmp_src = src0;
898 tmp_src.negate = ~tmp_src.negate;
899
900 emit(ir, OPCODE_ADD, dst_reg(difference), tmp_src, src1);
901 }
902
903 emit(ir, OPCODE_ABS, dst_reg(abs_difference), difference);
904
905 abs_difference.negate = ~abs_difference.negate;
906 emit(ir, op, dst, abs_difference, zero);
907 }
908
909 void
visit(ir_expression * ir)910 ir_to_mesa_visitor::visit(ir_expression *ir)
911 {
912 unsigned int operand;
913 src_reg op[ARRAY_SIZE(ir->operands)];
914 src_reg result_src;
915 dst_reg result_dst;
916
917 /* Quick peephole: Emit OPCODE_MAD(a, b, c) instead of ADD(MUL(a, b), c)
918 */
919 if (ir->operation == ir_binop_add) {
920 if (try_emit_mad(ir, 1))
921 return;
922 if (try_emit_mad(ir, 0))
923 return;
924 }
925
926 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
927 */
928 if (ir->operation == ir_binop_logic_and) {
929 if (try_emit_mad_for_and_not(ir, 1))
930 return;
931 if (try_emit_mad_for_and_not(ir, 0))
932 return;
933 }
934
935 if (ir->operation == ir_quadop_vector) {
936 this->emit_swz(ir);
937 return;
938 }
939
940 for (operand = 0; operand < ir->num_operands; operand++) {
941 this->result.file = PROGRAM_UNDEFINED;
942 ir->operands[operand]->accept(this);
943 if (this->result.file == PROGRAM_UNDEFINED) {
944 printf("Failed to get tree for expression operand:\n");
945 ir->operands[operand]->print();
946 printf("\n");
947 exit(1);
948 }
949 op[operand] = this->result;
950
951 /* Matrix expression operands should have been broken down to vector
952 * operations already.
953 */
954 assert(!ir->operands[operand]->type->is_matrix());
955 }
956
957 int vector_elements = ir->operands[0]->type->vector_elements;
958 if (ir->operands[1]) {
959 vector_elements = MAX2(vector_elements,
960 ir->operands[1]->type->vector_elements);
961 }
962
963 this->result.file = PROGRAM_UNDEFINED;
964
965 /* Storage for our result. Ideally for an assignment we'd be using
966 * the actual storage for the result here, instead.
967 */
968 result_src = get_temp(ir->type);
969 /* convenience for the emit functions below. */
970 result_dst = dst_reg(result_src);
971 /* Limit writes to the channels that will be used by result_src later.
972 * This does limit this temp's use as a temporary for multi-instruction
973 * sequences.
974 */
975 result_dst.writemask = (1 << ir->type->vector_elements) - 1;
976
977 switch (ir->operation) {
978 case ir_unop_logic_not:
979 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
980 * older GPUs implement SEQ using multiple instructions (i915 uses two
981 * SGE instructions and a MUL instruction). Since our logic values are
982 * 0.0 and 1.0, 1-x also implements !x.
983 */
984 op[0].negate = ~op[0].negate;
985 emit(ir, OPCODE_ADD, result_dst, op[0], src_reg_for_float(1.0));
986 break;
987 case ir_unop_neg:
988 op[0].negate = ~op[0].negate;
989 result_src = op[0];
990 break;
991 case ir_unop_abs:
992 emit(ir, OPCODE_ABS, result_dst, op[0]);
993 break;
994 case ir_unop_sign:
995 emit(ir, OPCODE_SSG, result_dst, op[0]);
996 break;
997 case ir_unop_rcp:
998 emit_scalar(ir, OPCODE_RCP, result_dst, op[0]);
999 break;
1000
1001 case ir_unop_exp2:
1002 emit_scalar(ir, OPCODE_EX2, result_dst, op[0]);
1003 break;
1004 case ir_unop_exp:
1005 assert(!"not reached: should be handled by exp_to_exp2");
1006 break;
1007 case ir_unop_log:
1008 assert(!"not reached: should be handled by log_to_log2");
1009 break;
1010 case ir_unop_log2:
1011 emit_scalar(ir, OPCODE_LG2, result_dst, op[0]);
1012 break;
1013 case ir_unop_sin:
1014 emit_scalar(ir, OPCODE_SIN, result_dst, op[0]);
1015 break;
1016 case ir_unop_cos:
1017 emit_scalar(ir, OPCODE_COS, result_dst, op[0]);
1018 break;
1019
1020 case ir_unop_dFdx:
1021 emit(ir, OPCODE_DDX, result_dst, op[0]);
1022 break;
1023 case ir_unop_dFdy:
1024 emit(ir, OPCODE_DDY, result_dst, op[0]);
1025 break;
1026
1027 case ir_unop_saturate: {
1028 ir_to_mesa_instruction *inst = emit(ir, OPCODE_MOV,
1029 result_dst, op[0]);
1030 inst->saturate = true;
1031 break;
1032 }
1033
1034 case ir_binop_add:
1035 emit(ir, OPCODE_ADD, result_dst, op[0], op[1]);
1036 break;
1037 case ir_binop_sub:
1038 emit(ir, OPCODE_SUB, result_dst, op[0], op[1]);
1039 break;
1040
1041 case ir_binop_mul:
1042 emit(ir, OPCODE_MUL, result_dst, op[0], op[1]);
1043 break;
1044 case ir_binop_div:
1045 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1046 break;
1047 case ir_binop_mod:
1048 /* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
1049 assert(ir->type->is_integer_32());
1050 emit(ir, OPCODE_MUL, result_dst, op[0], op[1]);
1051 break;
1052
1053 case ir_binop_less:
1054 emit(ir, OPCODE_SLT, result_dst, op[0], op[1]);
1055 break;
1056 case ir_binop_gequal:
1057 emit(ir, OPCODE_SGE, result_dst, op[0], op[1]);
1058 break;
1059 case ir_binop_equal:
1060 emit_seq(ir, result_dst, op[0], op[1]);
1061 break;
1062 case ir_binop_nequal:
1063 emit_sne(ir, result_dst, op[0], op[1]);
1064 break;
1065 case ir_binop_all_equal:
1066 /* "==" operator producing a scalar boolean. */
1067 if (ir->operands[0]->type->is_vector() ||
1068 ir->operands[1]->type->is_vector()) {
1069 src_reg temp = get_temp(glsl_type::vec4_type);
1070 emit_sne(ir, dst_reg(temp), op[0], op[1]);
1071
1072 /* After the dot-product, the value will be an integer on the
1073 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1074 */
1075 emit_dp(ir, result_dst, temp, temp, vector_elements);
1076
1077 /* Negating the result of the dot-product gives values on the range
1078 * [-4, 0]. Zero becomes 1.0, and negative values become zero. This
1079 * achieved using SGE.
1080 */
1081 src_reg sge_src = result_src;
1082 sge_src.negate = ~sge_src.negate;
1083 emit(ir, OPCODE_SGE, result_dst, sge_src, src_reg_for_float(0.0));
1084 } else {
1085 emit_seq(ir, result_dst, op[0], op[1]);
1086 }
1087 break;
1088 case ir_binop_any_nequal:
1089 /* "!=" operator producing a scalar boolean. */
1090 if (ir->operands[0]->type->is_vector() ||
1091 ir->operands[1]->type->is_vector()) {
1092 src_reg temp = get_temp(glsl_type::vec4_type);
1093 if (ir->operands[0]->type->is_boolean() &&
1094 ir->operands[1]->as_constant() &&
1095 ir->operands[1]->as_constant()->is_zero()) {
1096 temp = op[0];
1097 } else {
1098 emit_sne(ir, dst_reg(temp), op[0], op[1]);
1099 }
1100
1101 /* After the dot-product, the value will be an integer on the
1102 * range [0,4]. Zero stays zero, and positive values become 1.0.
1103 */
1104 ir_to_mesa_instruction *const dp =
1105 emit_dp(ir, result_dst, temp, temp, vector_elements);
1106 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1107 /* The clamping to [0,1] can be done for free in the fragment
1108 * shader with a saturate.
1109 */
1110 dp->saturate = true;
1111 } else {
1112 /* Negating the result of the dot-product gives values on the range
1113 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1114 * achieved using SLT.
1115 */
1116 src_reg slt_src = result_src;
1117 slt_src.negate = ~slt_src.negate;
1118 emit(ir, OPCODE_SLT, result_dst, slt_src, src_reg_for_float(0.0));
1119 }
1120 } else {
1121 emit_sne(ir, result_dst, op[0], op[1]);
1122 }
1123 break;
1124
1125 case ir_binop_logic_xor:
1126 emit_sne(ir, result_dst, op[0], op[1]);
1127 break;
1128
1129 case ir_binop_logic_or: {
1130 if (this->prog->Target == GL_FRAGMENT_PROGRAM_ARB) {
1131 /* After the addition, the value will be an integer on the
1132 * range [0,2]. Zero stays zero, and positive values become 1.0.
1133 */
1134 ir_to_mesa_instruction *add =
1135 emit(ir, OPCODE_ADD, result_dst, op[0], op[1]);
1136 add->saturate = true;
1137 } else {
1138 /* The Boolean arguments are stored as float 0.0 and 1.0. If either
1139 * value is 1.0, the result of the logcal-or should be 1.0. If both
1140 * values are 0.0, the result should be 0.0. This is exactly what
1141 * MAX does.
1142 */
1143 emit(ir, OPCODE_MAX, result_dst, op[0], op[1]);
1144 }
1145 break;
1146 }
1147
1148 case ir_binop_logic_and:
1149 /* the bool args are stored as float 0.0 or 1.0, so "mul" gives us "and". */
1150 emit(ir, OPCODE_MUL, result_dst, op[0], op[1]);
1151 break;
1152
1153 case ir_binop_dot:
1154 assert(ir->operands[0]->type->is_vector());
1155 assert(ir->operands[0]->type == ir->operands[1]->type);
1156 emit_dp(ir, result_dst, op[0], op[1],
1157 ir->operands[0]->type->vector_elements);
1158 break;
1159
1160 case ir_unop_sqrt:
1161 /* sqrt(x) = x * rsq(x). */
1162 emit_scalar(ir, OPCODE_RSQ, result_dst, op[0]);
1163 emit(ir, OPCODE_MUL, result_dst, result_src, op[0]);
1164 /* For incoming channels <= 0, set the result to 0. */
1165 op[0].negate = ~op[0].negate;
1166 emit(ir, OPCODE_CMP, result_dst,
1167 op[0], result_src, src_reg_for_float(0.0));
1168 break;
1169 case ir_unop_rsq:
1170 emit_scalar(ir, OPCODE_RSQ, result_dst, op[0]);
1171 break;
1172 case ir_unop_i2f:
1173 case ir_unop_u2f:
1174 case ir_unop_b2f:
1175 case ir_unop_b2i:
1176 case ir_unop_i2u:
1177 case ir_unop_u2i:
1178 /* Mesa IR lacks types, ints are stored as truncated floats. */
1179 result_src = op[0];
1180 break;
1181 case ir_unop_f2i:
1182 case ir_unop_f2u:
1183 emit(ir, OPCODE_TRUNC, result_dst, op[0]);
1184 break;
1185 case ir_unop_f2b:
1186 case ir_unop_i2b:
1187 emit_sne(ir, result_dst, op[0], src_reg_for_float(0.0));
1188 break;
1189 case ir_unop_bitcast_f2i: // Ignore these 4, they can't happen here anyway
1190 case ir_unop_bitcast_f2u:
1191 case ir_unop_bitcast_i2f:
1192 case ir_unop_bitcast_u2f:
1193 break;
1194 case ir_unop_trunc:
1195 emit(ir, OPCODE_TRUNC, result_dst, op[0]);
1196 break;
1197 case ir_unop_ceil:
1198 op[0].negate = ~op[0].negate;
1199 emit(ir, OPCODE_FLR, result_dst, op[0]);
1200 result_src.negate = ~result_src.negate;
1201 break;
1202 case ir_unop_floor:
1203 emit(ir, OPCODE_FLR, result_dst, op[0]);
1204 break;
1205 case ir_unop_fract:
1206 emit(ir, OPCODE_FRC, result_dst, op[0]);
1207 break;
1208 case ir_unop_pack_snorm_2x16:
1209 case ir_unop_pack_snorm_4x8:
1210 case ir_unop_pack_unorm_2x16:
1211 case ir_unop_pack_unorm_4x8:
1212 case ir_unop_pack_half_2x16:
1213 case ir_unop_pack_double_2x32:
1214 case ir_unop_unpack_snorm_2x16:
1215 case ir_unop_unpack_snorm_4x8:
1216 case ir_unop_unpack_unorm_2x16:
1217 case ir_unop_unpack_unorm_4x8:
1218 case ir_unop_unpack_half_2x16:
1219 case ir_unop_unpack_double_2x32:
1220 case ir_unop_bitfield_reverse:
1221 case ir_unop_bit_count:
1222 case ir_unop_find_msb:
1223 case ir_unop_find_lsb:
1224 case ir_unop_d2f:
1225 case ir_unop_f2d:
1226 case ir_unop_d2i:
1227 case ir_unop_i2d:
1228 case ir_unop_d2u:
1229 case ir_unop_u2d:
1230 case ir_unop_d2b:
1231 case ir_unop_frexp_sig:
1232 case ir_unop_frexp_exp:
1233 assert(!"not supported");
1234 break;
1235 case ir_binop_min:
1236 emit(ir, OPCODE_MIN, result_dst, op[0], op[1]);
1237 break;
1238 case ir_binop_max:
1239 emit(ir, OPCODE_MAX, result_dst, op[0], op[1]);
1240 break;
1241 case ir_binop_pow:
1242 emit_scalar(ir, OPCODE_POW, result_dst, op[0], op[1]);
1243 break;
1244
1245 /* GLSL 1.30 integer ops are unsupported in Mesa IR, but since
1246 * hardware backends have no way to avoid Mesa IR generation
1247 * even if they don't use it, we need to emit "something" and
1248 * continue.
1249 */
1250 case ir_binop_lshift:
1251 case ir_binop_rshift:
1252 case ir_binop_bit_and:
1253 case ir_binop_bit_xor:
1254 case ir_binop_bit_or:
1255 emit(ir, OPCODE_ADD, result_dst, op[0], op[1]);
1256 break;
1257
1258 case ir_unop_bit_not:
1259 case ir_unop_round_even:
1260 emit(ir, OPCODE_MOV, result_dst, op[0]);
1261 break;
1262
1263 case ir_binop_ubo_load:
1264 assert(!"not supported");
1265 break;
1266
1267 case ir_triop_lrp:
1268 /* ir_triop_lrp operands are (x, y, a) while
1269 * OPCODE_LRP operands are (a, y, x) to match ARB_fragment_program.
1270 */
1271 emit(ir, OPCODE_LRP, result_dst, op[2], op[1], op[0]);
1272 break;
1273
1274 case ir_triop_csel:
1275 /* We assume that boolean true and false are 1.0 and 0.0. OPCODE_CMP
1276 * selects src1 if src0 is < 0, src2 otherwise.
1277 */
1278 op[0].negate = ~op[0].negate;
1279 emit(ir, OPCODE_CMP, result_dst, op[0], op[1], op[2]);
1280 break;
1281
1282 case ir_binop_vector_extract:
1283 case ir_triop_fma:
1284 case ir_triop_bitfield_extract:
1285 case ir_triop_vector_insert:
1286 case ir_quadop_bitfield_insert:
1287 case ir_binop_ldexp:
1288 case ir_binop_carry:
1289 case ir_binop_borrow:
1290 case ir_binop_abs_sub:
1291 case ir_binop_add_sat:
1292 case ir_binop_sub_sat:
1293 case ir_binop_avg:
1294 case ir_binop_avg_round:
1295 case ir_binop_mul_32x16:
1296 case ir_binop_imul_high:
1297 case ir_unop_interpolate_at_centroid:
1298 case ir_binop_interpolate_at_offset:
1299 case ir_binop_interpolate_at_sample:
1300 case ir_unop_dFdx_coarse:
1301 case ir_unop_dFdx_fine:
1302 case ir_unop_dFdy_coarse:
1303 case ir_unop_dFdy_fine:
1304 case ir_unop_subroutine_to_int:
1305 case ir_unop_get_buffer_size:
1306 case ir_unop_bitcast_u642d:
1307 case ir_unop_bitcast_i642d:
1308 case ir_unop_bitcast_d2u64:
1309 case ir_unop_bitcast_d2i64:
1310 case ir_unop_i642i:
1311 case ir_unop_u642i:
1312 case ir_unop_i642u:
1313 case ir_unop_u642u:
1314 case ir_unop_i642b:
1315 case ir_unop_i642f:
1316 case ir_unop_u642f:
1317 case ir_unop_i642d:
1318 case ir_unop_u642d:
1319 case ir_unop_i2i64:
1320 case ir_unop_u2i64:
1321 case ir_unop_b2i64:
1322 case ir_unop_f2i64:
1323 case ir_unop_d2i64:
1324 case ir_unop_i2u64:
1325 case ir_unop_u2u64:
1326 case ir_unop_f2u64:
1327 case ir_unop_d2u64:
1328 case ir_unop_u642i64:
1329 case ir_unop_i642u64:
1330 case ir_unop_pack_int_2x32:
1331 case ir_unop_unpack_int_2x32:
1332 case ir_unop_pack_uint_2x32:
1333 case ir_unop_unpack_uint_2x32:
1334 case ir_unop_pack_sampler_2x32:
1335 case ir_unop_unpack_sampler_2x32:
1336 case ir_unop_pack_image_2x32:
1337 case ir_unop_unpack_image_2x32:
1338 case ir_unop_atan:
1339 case ir_binop_atan2:
1340 case ir_unop_clz:
1341 case ir_unop_f162f:
1342 case ir_unop_f2f16:
1343 case ir_unop_f2fmp:
1344 case ir_unop_f162b:
1345 case ir_unop_b2f16:
1346 case ir_unop_i2i:
1347 case ir_unop_i2imp:
1348 case ir_unop_u2u:
1349 case ir_unop_u2ump:
1350 assert(!"not supported");
1351 break;
1352
1353 case ir_unop_ssbo_unsized_array_length:
1354 case ir_quadop_vector:
1355 /* This operation should have already been handled.
1356 */
1357 assert(!"Should not get here.");
1358 break;
1359 }
1360
1361 this->result = result_src;
1362 }
1363
1364
1365 void
visit(ir_swizzle * ir)1366 ir_to_mesa_visitor::visit(ir_swizzle *ir)
1367 {
1368 src_reg src;
1369 int i;
1370 int swizzle[4] = {0};
1371
1372 /* Note that this is only swizzles in expressions, not those on the left
1373 * hand side of an assignment, which do write masking. See ir_assignment
1374 * for that.
1375 */
1376
1377 ir->val->accept(this);
1378 src = this->result;
1379 assert(src.file != PROGRAM_UNDEFINED);
1380 assert(ir->type->vector_elements > 0);
1381
1382 for (i = 0; i < 4; i++) {
1383 if (i < ir->type->vector_elements) {
1384 switch (i) {
1385 case 0:
1386 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.x);
1387 break;
1388 case 1:
1389 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.y);
1390 break;
1391 case 2:
1392 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.z);
1393 break;
1394 case 3:
1395 swizzle[i] = GET_SWZ(src.swizzle, ir->mask.w);
1396 break;
1397 }
1398 } else {
1399 /* If the type is smaller than a vec4, replicate the last
1400 * channel out.
1401 */
1402 swizzle[i] = swizzle[ir->type->vector_elements - 1];
1403 }
1404 }
1405
1406 src.swizzle = MAKE_SWIZZLE4(swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
1407
1408 this->result = src;
1409 }
1410
1411 void
visit(ir_dereference_variable * ir)1412 ir_to_mesa_visitor::visit(ir_dereference_variable *ir)
1413 {
1414 variable_storage *entry = find_variable_storage(ir->var);
1415 ir_variable *var = ir->var;
1416
1417 if (!entry) {
1418 switch (var->data.mode) {
1419 case ir_var_uniform:
1420 entry = new(mem_ctx) variable_storage(var, PROGRAM_UNIFORM,
1421 var->data.param_index);
1422 this->variables.push_tail(entry);
1423 break;
1424 case ir_var_shader_in:
1425 /* The linker assigns locations for varyings and attributes,
1426 * including deprecated builtins (like gl_Color),
1427 * user-assigned generic attributes (glBindVertexLocation),
1428 * and user-defined varyings.
1429 */
1430 assert(var->data.location != -1);
1431 entry = new(mem_ctx) variable_storage(var,
1432 PROGRAM_INPUT,
1433 var->data.location);
1434 break;
1435 case ir_var_shader_out:
1436 assert(var->data.location != -1);
1437 entry = new(mem_ctx) variable_storage(var,
1438 PROGRAM_OUTPUT,
1439 var->data.location);
1440 break;
1441 case ir_var_system_value:
1442 entry = new(mem_ctx) variable_storage(var,
1443 PROGRAM_SYSTEM_VALUE,
1444 var->data.location);
1445 break;
1446 case ir_var_auto:
1447 case ir_var_temporary:
1448 entry = new(mem_ctx) variable_storage(var, PROGRAM_TEMPORARY,
1449 this->next_temp);
1450 this->variables.push_tail(entry);
1451
1452 next_temp += type_size(var->type);
1453 break;
1454 }
1455
1456 if (!entry) {
1457 printf("Failed to make storage for %s\n", var->name);
1458 exit(1);
1459 }
1460 }
1461
1462 this->result = src_reg(entry->file, entry->index, var->type);
1463 }
1464
1465 void
visit(ir_dereference_array * ir)1466 ir_to_mesa_visitor::visit(ir_dereference_array *ir)
1467 {
1468 ir_constant *index;
1469 src_reg src;
1470 int element_size = type_size(ir->type);
1471
1472 index = ir->array_index->constant_expression_value(ralloc_parent(ir));
1473
1474 ir->array->accept(this);
1475 src = this->result;
1476
1477 if (index) {
1478 src.index += index->value.i[0] * element_size;
1479 } else {
1480 /* Variable index array dereference. It eats the "vec4" of the
1481 * base of the array and an index that offsets the Mesa register
1482 * index.
1483 */
1484 ir->array_index->accept(this);
1485
1486 src_reg index_reg;
1487
1488 if (element_size == 1) {
1489 index_reg = this->result;
1490 } else {
1491 index_reg = get_temp(glsl_type::float_type);
1492
1493 emit(ir, OPCODE_MUL, dst_reg(index_reg),
1494 this->result, src_reg_for_float(element_size));
1495 }
1496
1497 /* If there was already a relative address register involved, add the
1498 * new and the old together to get the new offset.
1499 */
1500 if (src.reladdr != NULL) {
1501 src_reg accum_reg = get_temp(glsl_type::float_type);
1502
1503 emit(ir, OPCODE_ADD, dst_reg(accum_reg),
1504 index_reg, *src.reladdr);
1505
1506 index_reg = accum_reg;
1507 }
1508
1509 src.reladdr = ralloc(mem_ctx, src_reg);
1510 memcpy(src.reladdr, &index_reg, sizeof(index_reg));
1511 }
1512
1513 /* If the type is smaller than a vec4, replicate the last channel out. */
1514 if (ir->type->is_scalar() || ir->type->is_vector())
1515 src.swizzle = swizzle_for_size(ir->type->vector_elements);
1516 else
1517 src.swizzle = SWIZZLE_NOOP;
1518
1519 this->result = src;
1520 }
1521
1522 void
visit(ir_dereference_record * ir)1523 ir_to_mesa_visitor::visit(ir_dereference_record *ir)
1524 {
1525 unsigned int i;
1526 const glsl_type *struct_type = ir->record->type;
1527 int offset = 0;
1528
1529 ir->record->accept(this);
1530
1531 assert(ir->field_idx >= 0);
1532 for (i = 0; i < struct_type->length; i++) {
1533 if (i == (unsigned) ir->field_idx)
1534 break;
1535 offset += type_size(struct_type->fields.structure[i].type);
1536 }
1537
1538 /* If the type is smaller than a vec4, replicate the last channel out. */
1539 if (ir->type->is_scalar() || ir->type->is_vector())
1540 this->result.swizzle = swizzle_for_size(ir->type->vector_elements);
1541 else
1542 this->result.swizzle = SWIZZLE_NOOP;
1543
1544 this->result.index += offset;
1545 }
1546
1547 /**
1548 * We want to be careful in assignment setup to hit the actual storage
1549 * instead of potentially using a temporary like we might with the
1550 * ir_dereference handler.
1551 */
1552 static dst_reg
get_assignment_lhs(ir_dereference * ir,ir_to_mesa_visitor * v)1553 get_assignment_lhs(ir_dereference *ir, ir_to_mesa_visitor *v)
1554 {
1555 /* The LHS must be a dereference. If the LHS is a variable indexed array
1556 * access of a vector, it must be separated into a series conditional moves
1557 * before reaching this point (see ir_vec_index_to_cond_assign).
1558 */
1559 assert(ir->as_dereference());
1560 ir_dereference_array *deref_array = ir->as_dereference_array();
1561 if (deref_array) {
1562 assert(!deref_array->array->type->is_vector());
1563 }
1564
1565 /* Use the rvalue deref handler for the most part. We'll ignore
1566 * swizzles in it and write swizzles using writemask, though.
1567 */
1568 ir->accept(v);
1569 return dst_reg(v->result);
1570 }
1571
1572 /* Calculate the sampler index and also calculate the base uniform location
1573 * for struct members.
1574 */
1575 static void
calc_sampler_offsets(struct gl_shader_program * prog,ir_dereference * deref,unsigned * offset,unsigned * array_elements,unsigned * location)1576 calc_sampler_offsets(struct gl_shader_program *prog, ir_dereference *deref,
1577 unsigned *offset, unsigned *array_elements,
1578 unsigned *location)
1579 {
1580 if (deref->ir_type == ir_type_dereference_variable)
1581 return;
1582
1583 switch (deref->ir_type) {
1584 case ir_type_dereference_array: {
1585 ir_dereference_array *deref_arr = deref->as_dereference_array();
1586
1587 void *mem_ctx = ralloc_parent(deref_arr);
1588 ir_constant *array_index =
1589 deref_arr->array_index->constant_expression_value(mem_ctx);
1590
1591 if (!array_index) {
1592 /* GLSL 1.10 and 1.20 allowed variable sampler array indices,
1593 * while GLSL 1.30 requires that the array indices be
1594 * constant integer expressions. We don't expect any driver
1595 * to actually work with a really variable array index, so
1596 * all that would work would be an unrolled loop counter that ends
1597 * up being constant above.
1598 */
1599 ralloc_strcat(&prog->data->InfoLog,
1600 "warning: Variable sampler array index unsupported.\n"
1601 "This feature of the language was removed in GLSL 1.20 "
1602 "and is unlikely to be supported for 1.10 in Mesa.\n");
1603 } else {
1604 *offset += array_index->value.u[0] * *array_elements;
1605 }
1606
1607 *array_elements *= deref_arr->array->type->length;
1608
1609 calc_sampler_offsets(prog, deref_arr->array->as_dereference(),
1610 offset, array_elements, location);
1611 break;
1612 }
1613
1614 case ir_type_dereference_record: {
1615 ir_dereference_record *deref_record = deref->as_dereference_record();
1616 unsigned field_index = deref_record->field_idx;
1617 *location +=
1618 deref_record->record->type->struct_location_offset(field_index);
1619 calc_sampler_offsets(prog, deref_record->record->as_dereference(),
1620 offset, array_elements, location);
1621 break;
1622 }
1623
1624 default:
1625 unreachable("Invalid deref type");
1626 break;
1627 }
1628 }
1629
1630 static int
get_sampler_uniform_value(class ir_dereference * sampler,struct gl_shader_program * shader_program,const struct gl_program * prog)1631 get_sampler_uniform_value(class ir_dereference *sampler,
1632 struct gl_shader_program *shader_program,
1633 const struct gl_program *prog)
1634 {
1635 GLuint shader = _mesa_program_enum_to_shader_stage(prog->Target);
1636 ir_variable *var = sampler->variable_referenced();
1637 unsigned location = var->data.location;
1638 unsigned array_elements = 1;
1639 unsigned offset = 0;
1640
1641 calc_sampler_offsets(shader_program, sampler, &offset, &array_elements,
1642 &location);
1643
1644 assert(shader_program->data->UniformStorage[location].opaque[shader].active);
1645 return shader_program->data->UniformStorage[location].opaque[shader].index +
1646 offset;
1647 }
1648
1649 /**
1650 * Process the condition of a conditional assignment
1651 *
1652 * Examines the condition of a conditional assignment to generate the optimal
1653 * first operand of a \c CMP instruction. If the condition is a relational
1654 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
1655 * used as the source for the \c CMP instruction. Otherwise the comparison
1656 * is processed to a boolean result, and the boolean result is used as the
1657 * operand to the CMP instruction.
1658 */
1659 bool
process_move_condition(ir_rvalue * ir)1660 ir_to_mesa_visitor::process_move_condition(ir_rvalue *ir)
1661 {
1662 ir_rvalue *src_ir = ir;
1663 bool negate = true;
1664 bool switch_order = false;
1665
1666 ir_expression *const expr = ir->as_expression();
1667 if ((expr != NULL) && (expr->num_operands == 2)) {
1668 bool zero_on_left = false;
1669
1670 if (expr->operands[0]->is_zero()) {
1671 src_ir = expr->operands[1];
1672 zero_on_left = true;
1673 } else if (expr->operands[1]->is_zero()) {
1674 src_ir = expr->operands[0];
1675 zero_on_left = false;
1676 }
1677
1678 /* a is - 0 + - 0 +
1679 * (a < 0) T F F ( a < 0) T F F
1680 * (0 < a) F F T (-a < 0) F F T
1681 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
1682 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
1683 *
1684 * Note that exchanging the order of 0 and 'a' in the comparison simply
1685 * means that the value of 'a' should be negated.
1686 */
1687 if (src_ir != ir) {
1688 switch (expr->operation) {
1689 case ir_binop_less:
1690 switch_order = false;
1691 negate = zero_on_left;
1692 break;
1693
1694 case ir_binop_gequal:
1695 switch_order = true;
1696 negate = zero_on_left;
1697 break;
1698
1699 default:
1700 /* This isn't the right kind of comparison afterall, so make sure
1701 * the whole condition is visited.
1702 */
1703 src_ir = ir;
1704 break;
1705 }
1706 }
1707 }
1708
1709 src_ir->accept(this);
1710
1711 /* We use the OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
1712 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
1713 * choose which value OPCODE_CMP produces without an extra instruction
1714 * computing the condition.
1715 */
1716 if (negate)
1717 this->result.negate = ~this->result.negate;
1718
1719 return switch_order;
1720 }
1721
1722 void
visit(ir_assignment * ir)1723 ir_to_mesa_visitor::visit(ir_assignment *ir)
1724 {
1725 dst_reg l;
1726 src_reg r;
1727 int i;
1728
1729 ir->rhs->accept(this);
1730 r = this->result;
1731
1732 l = get_assignment_lhs(ir->lhs, this);
1733
1734 /* FINISHME: This should really set to the correct maximal writemask for each
1735 * FINISHME: component written (in the loops below). This case can only
1736 * FINISHME: occur for matrices, arrays, and structures.
1737 */
1738 if (ir->write_mask == 0) {
1739 assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
1740 l.writemask = WRITEMASK_XYZW;
1741 } else if (ir->lhs->type->is_scalar()) {
1742 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
1743 * FINISHME: W component of fragment shader output zero, work correctly.
1744 */
1745 l.writemask = WRITEMASK_XYZW;
1746 } else {
1747 int swizzles[4];
1748 int first_enabled_chan = 0;
1749 int rhs_chan = 0;
1750
1751 assert(ir->lhs->type->is_vector());
1752 l.writemask = ir->write_mask;
1753
1754 for (int i = 0; i < 4; i++) {
1755 if (l.writemask & (1 << i)) {
1756 first_enabled_chan = GET_SWZ(r.swizzle, i);
1757 break;
1758 }
1759 }
1760
1761 /* Swizzle a small RHS vector into the channels being written.
1762 *
1763 * glsl ir treats write_mask as dictating how many channels are
1764 * present on the RHS while Mesa IR treats write_mask as just
1765 * showing which channels of the vec4 RHS get written.
1766 */
1767 for (int i = 0; i < 4; i++) {
1768 if (l.writemask & (1 << i))
1769 swizzles[i] = GET_SWZ(r.swizzle, rhs_chan++);
1770 else
1771 swizzles[i] = first_enabled_chan;
1772 }
1773 r.swizzle = MAKE_SWIZZLE4(swizzles[0], swizzles[1],
1774 swizzles[2], swizzles[3]);
1775 }
1776
1777 assert(l.file != PROGRAM_UNDEFINED);
1778 assert(r.file != PROGRAM_UNDEFINED);
1779
1780 if (ir->condition) {
1781 const bool switch_order = this->process_move_condition(ir->condition);
1782 src_reg condition = this->result;
1783
1784 for (i = 0; i < type_size(ir->lhs->type); i++) {
1785 if (switch_order) {
1786 emit(ir, OPCODE_CMP, l, condition, src_reg(l), r);
1787 } else {
1788 emit(ir, OPCODE_CMP, l, condition, r, src_reg(l));
1789 }
1790
1791 l.index++;
1792 r.index++;
1793 }
1794 } else {
1795 for (i = 0; i < type_size(ir->lhs->type); i++) {
1796 emit(ir, OPCODE_MOV, l, r);
1797 l.index++;
1798 r.index++;
1799 }
1800 }
1801 }
1802
1803
1804 void
visit(ir_constant * ir)1805 ir_to_mesa_visitor::visit(ir_constant *ir)
1806 {
1807 src_reg src;
1808 GLfloat stack_vals[4] = { 0 };
1809 GLfloat *values = stack_vals;
1810 unsigned int i;
1811
1812 /* Unfortunately, 4 floats is all we can get into
1813 * _mesa_add_unnamed_constant. So, make a temp to store an
1814 * aggregate constant and move each constant value into it. If we
1815 * get lucky, copy propagation will eliminate the extra moves.
1816 */
1817
1818 if (ir->type->is_struct()) {
1819 src_reg temp_base = get_temp(ir->type);
1820 dst_reg temp = dst_reg(temp_base);
1821
1822 for (i = 0; i < ir->type->length; i++) {
1823 ir_constant *const field_value = ir->get_record_field(i);
1824 int size = type_size(field_value->type);
1825
1826 assert(size > 0);
1827
1828 field_value->accept(this);
1829 src = this->result;
1830
1831 for (unsigned j = 0; j < (unsigned int)size; j++) {
1832 emit(ir, OPCODE_MOV, temp, src);
1833
1834 src.index++;
1835 temp.index++;
1836 }
1837 }
1838 this->result = temp_base;
1839 return;
1840 }
1841
1842 if (ir->type->is_array()) {
1843 src_reg temp_base = get_temp(ir->type);
1844 dst_reg temp = dst_reg(temp_base);
1845 int size = type_size(ir->type->fields.array);
1846
1847 assert(size > 0);
1848
1849 for (i = 0; i < ir->type->length; i++) {
1850 ir->const_elements[i]->accept(this);
1851 src = this->result;
1852 for (int j = 0; j < size; j++) {
1853 emit(ir, OPCODE_MOV, temp, src);
1854
1855 src.index++;
1856 temp.index++;
1857 }
1858 }
1859 this->result = temp_base;
1860 return;
1861 }
1862
1863 if (ir->type->is_matrix()) {
1864 src_reg mat = get_temp(ir->type);
1865 dst_reg mat_column = dst_reg(mat);
1866
1867 for (i = 0; i < ir->type->matrix_columns; i++) {
1868 assert(ir->type->is_float());
1869 values = &ir->value.f[i * ir->type->vector_elements];
1870
1871 src = src_reg(PROGRAM_CONSTANT, -1, NULL);
1872 src.index = _mesa_add_unnamed_constant(this->prog->Parameters,
1873 (gl_constant_value *) values,
1874 ir->type->vector_elements,
1875 &src.swizzle);
1876 emit(ir, OPCODE_MOV, mat_column, src);
1877
1878 mat_column.index++;
1879 }
1880
1881 this->result = mat;
1882 return;
1883 }
1884
1885 src.file = PROGRAM_CONSTANT;
1886 switch (ir->type->base_type) {
1887 case GLSL_TYPE_FLOAT:
1888 values = &ir->value.f[0];
1889 break;
1890 case GLSL_TYPE_UINT:
1891 for (i = 0; i < ir->type->vector_elements; i++) {
1892 values[i] = ir->value.u[i];
1893 }
1894 break;
1895 case GLSL_TYPE_INT:
1896 for (i = 0; i < ir->type->vector_elements; i++) {
1897 values[i] = ir->value.i[i];
1898 }
1899 break;
1900 case GLSL_TYPE_BOOL:
1901 for (i = 0; i < ir->type->vector_elements; i++) {
1902 values[i] = ir->value.b[i];
1903 }
1904 break;
1905 default:
1906 assert(!"Non-float/uint/int/bool constant");
1907 }
1908
1909 this->result = src_reg(PROGRAM_CONSTANT, -1, ir->type);
1910 this->result.index = _mesa_add_unnamed_constant(this->prog->Parameters,
1911 (gl_constant_value *) values,
1912 ir->type->vector_elements,
1913 &this->result.swizzle);
1914 }
1915
1916 void
visit(ir_call *)1917 ir_to_mesa_visitor::visit(ir_call *)
1918 {
1919 assert(!"ir_to_mesa: All function calls should have been inlined by now.");
1920 }
1921
1922 void
visit(ir_texture * ir)1923 ir_to_mesa_visitor::visit(ir_texture *ir)
1924 {
1925 src_reg result_src, coord, lod_info, projector, dx, dy;
1926 dst_reg result_dst, coord_dst;
1927 ir_to_mesa_instruction *inst = NULL;
1928 prog_opcode opcode = OPCODE_NOP;
1929
1930 if (ir->op == ir_txs)
1931 this->result = src_reg_for_float(0.0);
1932 else
1933 ir->coordinate->accept(this);
1934
1935 /* Put our coords in a temp. We'll need to modify them for shadow,
1936 * projection, or LOD, so the only case we'd use it as-is is if
1937 * we're doing plain old texturing. Mesa IR optimization should
1938 * handle cleaning up our mess in that case.
1939 */
1940 coord = get_temp(glsl_type::vec4_type);
1941 coord_dst = dst_reg(coord);
1942 emit(ir, OPCODE_MOV, coord_dst, this->result);
1943
1944 if (ir->projector) {
1945 ir->projector->accept(this);
1946 projector = this->result;
1947 }
1948
1949 /* Storage for our result. Ideally for an assignment we'd be using
1950 * the actual storage for the result here, instead.
1951 */
1952 result_src = get_temp(glsl_type::vec4_type);
1953 result_dst = dst_reg(result_src);
1954
1955 switch (ir->op) {
1956 case ir_tex:
1957 case ir_txs:
1958 opcode = OPCODE_TEX;
1959 break;
1960 case ir_txb:
1961 opcode = OPCODE_TXB;
1962 ir->lod_info.bias->accept(this);
1963 lod_info = this->result;
1964 break;
1965 case ir_txf:
1966 /* Pretend to be TXL so the sampler, coordinate, lod are available */
1967 case ir_txl:
1968 opcode = OPCODE_TXL;
1969 ir->lod_info.lod->accept(this);
1970 lod_info = this->result;
1971 break;
1972 case ir_txd:
1973 opcode = OPCODE_TXD;
1974 ir->lod_info.grad.dPdx->accept(this);
1975 dx = this->result;
1976 ir->lod_info.grad.dPdy->accept(this);
1977 dy = this->result;
1978 break;
1979 case ir_txf_ms:
1980 assert(!"Unexpected ir_txf_ms opcode");
1981 break;
1982 case ir_lod:
1983 assert(!"Unexpected ir_lod opcode");
1984 break;
1985 case ir_tg4:
1986 assert(!"Unexpected ir_tg4 opcode");
1987 break;
1988 case ir_query_levels:
1989 assert(!"Unexpected ir_query_levels opcode");
1990 break;
1991 case ir_samples_identical:
1992 unreachable("Unexpected ir_samples_identical opcode");
1993 case ir_texture_samples:
1994 unreachable("Unexpected ir_texture_samples opcode");
1995 }
1996
1997 const glsl_type *sampler_type = ir->sampler->type;
1998
1999 if (ir->projector) {
2000 if (opcode == OPCODE_TEX) {
2001 /* Slot the projector in as the last component of the coord. */
2002 coord_dst.writemask = WRITEMASK_W;
2003 emit(ir, OPCODE_MOV, coord_dst, projector);
2004 coord_dst.writemask = WRITEMASK_XYZW;
2005 opcode = OPCODE_TXP;
2006 } else {
2007 src_reg coord_w = coord;
2008 coord_w.swizzle = SWIZZLE_WWWW;
2009
2010 /* For the other TEX opcodes there's no projective version
2011 * since the last slot is taken up by lod info. Do the
2012 * projective divide now.
2013 */
2014 coord_dst.writemask = WRITEMASK_W;
2015 emit(ir, OPCODE_RCP, coord_dst, projector);
2016
2017 /* In the case where we have to project the coordinates "by hand,"
2018 * the shadow comparator value must also be projected.
2019 */
2020 src_reg tmp_src = coord;
2021 if (ir->shadow_comparator) {
2022 /* Slot the shadow value in as the second to last component of the
2023 * coord.
2024 */
2025 ir->shadow_comparator->accept(this);
2026
2027 tmp_src = get_temp(glsl_type::vec4_type);
2028 dst_reg tmp_dst = dst_reg(tmp_src);
2029
2030 /* Projective division not allowed for array samplers. */
2031 assert(!sampler_type->sampler_array);
2032
2033 tmp_dst.writemask = WRITEMASK_Z;
2034 emit(ir, OPCODE_MOV, tmp_dst, this->result);
2035
2036 tmp_dst.writemask = WRITEMASK_XY;
2037 emit(ir, OPCODE_MOV, tmp_dst, coord);
2038 }
2039
2040 coord_dst.writemask = WRITEMASK_XYZ;
2041 emit(ir, OPCODE_MUL, coord_dst, tmp_src, coord_w);
2042
2043 coord_dst.writemask = WRITEMASK_XYZW;
2044 coord.swizzle = SWIZZLE_XYZW;
2045 }
2046 }
2047
2048 /* If projection is done and the opcode is not OPCODE_TXP, then the shadow
2049 * comparator was put in the correct place (and projected) by the code,
2050 * above, that handles by-hand projection.
2051 */
2052 if (ir->shadow_comparator && (!ir->projector || opcode == OPCODE_TXP)) {
2053 /* Slot the shadow value in as the second to last component of the
2054 * coord.
2055 */
2056 ir->shadow_comparator->accept(this);
2057
2058 /* XXX This will need to be updated for cubemap array samplers. */
2059 if (sampler_type->sampler_dimensionality == GLSL_SAMPLER_DIM_2D &&
2060 sampler_type->sampler_array) {
2061 coord_dst.writemask = WRITEMASK_W;
2062 } else {
2063 coord_dst.writemask = WRITEMASK_Z;
2064 }
2065
2066 emit(ir, OPCODE_MOV, coord_dst, this->result);
2067 coord_dst.writemask = WRITEMASK_XYZW;
2068 }
2069
2070 if (opcode == OPCODE_TXL || opcode == OPCODE_TXB) {
2071 /* Mesa IR stores lod or lod bias in the last channel of the coords. */
2072 coord_dst.writemask = WRITEMASK_W;
2073 emit(ir, OPCODE_MOV, coord_dst, lod_info);
2074 coord_dst.writemask = WRITEMASK_XYZW;
2075 }
2076
2077 if (opcode == OPCODE_TXD)
2078 inst = emit(ir, opcode, result_dst, coord, dx, dy);
2079 else
2080 inst = emit(ir, opcode, result_dst, coord);
2081
2082 if (ir->shadow_comparator)
2083 inst->tex_shadow = GL_TRUE;
2084
2085 inst->sampler = get_sampler_uniform_value(ir->sampler, shader_program,
2086 prog);
2087
2088 switch (sampler_type->sampler_dimensionality) {
2089 case GLSL_SAMPLER_DIM_1D:
2090 inst->tex_target = (sampler_type->sampler_array)
2091 ? TEXTURE_1D_ARRAY_INDEX : TEXTURE_1D_INDEX;
2092 break;
2093 case GLSL_SAMPLER_DIM_2D:
2094 inst->tex_target = (sampler_type->sampler_array)
2095 ? TEXTURE_2D_ARRAY_INDEX : TEXTURE_2D_INDEX;
2096 break;
2097 case GLSL_SAMPLER_DIM_3D:
2098 inst->tex_target = TEXTURE_3D_INDEX;
2099 break;
2100 case GLSL_SAMPLER_DIM_CUBE:
2101 inst->tex_target = TEXTURE_CUBE_INDEX;
2102 break;
2103 case GLSL_SAMPLER_DIM_RECT:
2104 inst->tex_target = TEXTURE_RECT_INDEX;
2105 break;
2106 case GLSL_SAMPLER_DIM_BUF:
2107 assert(!"FINISHME: Implement ARB_texture_buffer_object");
2108 break;
2109 case GLSL_SAMPLER_DIM_EXTERNAL:
2110 inst->tex_target = TEXTURE_EXTERNAL_INDEX;
2111 break;
2112 default:
2113 assert(!"Should not get here.");
2114 }
2115
2116 this->result = result_src;
2117 }
2118
2119 void
visit(ir_return * ir)2120 ir_to_mesa_visitor::visit(ir_return *ir)
2121 {
2122 /* Non-void functions should have been inlined. We may still emit RETs
2123 * from main() unless the EmitNoMainReturn option is set.
2124 */
2125 assert(!ir->get_value());
2126 emit(ir, OPCODE_RET);
2127 }
2128
2129 void
visit(ir_discard * ir)2130 ir_to_mesa_visitor::visit(ir_discard *ir)
2131 {
2132 if (!ir->condition)
2133 ir->condition = new(mem_ctx) ir_constant(true);
2134
2135 ir->condition->accept(this);
2136 this->result.negate = ~this->result.negate;
2137 emit(ir, OPCODE_KIL, undef_dst, this->result);
2138 }
2139
2140 void
visit(ir_demote * ir)2141 ir_to_mesa_visitor::visit(ir_demote *ir)
2142 {
2143 assert(!"demote statement unsupported");
2144 }
2145
2146 void
visit(ir_if * ir)2147 ir_to_mesa_visitor::visit(ir_if *ir)
2148 {
2149 ir_to_mesa_instruction *if_inst;
2150
2151 ir->condition->accept(this);
2152 assert(this->result.file != PROGRAM_UNDEFINED);
2153
2154 if_inst = emit(ir->condition, OPCODE_IF, undef_dst, this->result);
2155
2156 this->instructions.push_tail(if_inst);
2157
2158 visit_exec_list(&ir->then_instructions, this);
2159
2160 if (!ir->else_instructions.is_empty()) {
2161 emit(ir->condition, OPCODE_ELSE);
2162 visit_exec_list(&ir->else_instructions, this);
2163 }
2164
2165 emit(ir->condition, OPCODE_ENDIF);
2166 }
2167
2168 void
visit(ir_emit_vertex *)2169 ir_to_mesa_visitor::visit(ir_emit_vertex *)
2170 {
2171 assert(!"Geometry shaders not supported.");
2172 }
2173
2174 void
visit(ir_end_primitive *)2175 ir_to_mesa_visitor::visit(ir_end_primitive *)
2176 {
2177 assert(!"Geometry shaders not supported.");
2178 }
2179
2180 void
visit(ir_barrier *)2181 ir_to_mesa_visitor::visit(ir_barrier *)
2182 {
2183 unreachable("GLSL barrier() not supported.");
2184 }
2185
ir_to_mesa_visitor()2186 ir_to_mesa_visitor::ir_to_mesa_visitor()
2187 {
2188 result.file = PROGRAM_UNDEFINED;
2189 next_temp = 1;
2190 next_signature_id = 1;
2191 current_function = NULL;
2192 mem_ctx = ralloc_context(NULL);
2193 ctx = NULL;
2194 prog = NULL;
2195 shader_program = NULL;
2196 options = NULL;
2197 }
2198
~ir_to_mesa_visitor()2199 ir_to_mesa_visitor::~ir_to_mesa_visitor()
2200 {
2201 ralloc_free(mem_ctx);
2202 }
2203
2204 static struct prog_src_register
mesa_src_reg_from_ir_src_reg(src_reg reg)2205 mesa_src_reg_from_ir_src_reg(src_reg reg)
2206 {
2207 struct prog_src_register mesa_reg;
2208
2209 mesa_reg.File = reg.file;
2210 assert(reg.index < (1 << INST_INDEX_BITS));
2211 mesa_reg.Index = reg.index;
2212 mesa_reg.Swizzle = reg.swizzle;
2213 mesa_reg.RelAddr = reg.reladdr != NULL;
2214 mesa_reg.Negate = reg.negate;
2215
2216 return mesa_reg;
2217 }
2218
2219 static void
set_branchtargets(ir_to_mesa_visitor * v,struct prog_instruction * mesa_instructions,int num_instructions)2220 set_branchtargets(ir_to_mesa_visitor *v,
2221 struct prog_instruction *mesa_instructions,
2222 int num_instructions)
2223 {
2224 int if_count = 0, loop_count = 0;
2225 int *if_stack, *loop_stack;
2226 int if_stack_pos = 0, loop_stack_pos = 0;
2227 int i, j;
2228
2229 for (i = 0; i < num_instructions; i++) {
2230 switch (mesa_instructions[i].Opcode) {
2231 case OPCODE_IF:
2232 if_count++;
2233 break;
2234 case OPCODE_BGNLOOP:
2235 loop_count++;
2236 break;
2237 case OPCODE_BRK:
2238 case OPCODE_CONT:
2239 mesa_instructions[i].BranchTarget = -1;
2240 break;
2241 default:
2242 break;
2243 }
2244 }
2245
2246 if_stack = rzalloc_array(v->mem_ctx, int, if_count);
2247 loop_stack = rzalloc_array(v->mem_ctx, int, loop_count);
2248
2249 for (i = 0; i < num_instructions; i++) {
2250 switch (mesa_instructions[i].Opcode) {
2251 case OPCODE_IF:
2252 if_stack[if_stack_pos] = i;
2253 if_stack_pos++;
2254 break;
2255 case OPCODE_ELSE:
2256 mesa_instructions[if_stack[if_stack_pos - 1]].BranchTarget = i;
2257 if_stack[if_stack_pos - 1] = i;
2258 break;
2259 case OPCODE_ENDIF:
2260 mesa_instructions[if_stack[if_stack_pos - 1]].BranchTarget = i;
2261 if_stack_pos--;
2262 break;
2263 case OPCODE_BGNLOOP:
2264 loop_stack[loop_stack_pos] = i;
2265 loop_stack_pos++;
2266 break;
2267 case OPCODE_ENDLOOP:
2268 loop_stack_pos--;
2269 /* Rewrite any breaks/conts at this nesting level (haven't
2270 * already had a BranchTarget assigned) to point to the end
2271 * of the loop.
2272 */
2273 for (j = loop_stack[loop_stack_pos]; j < i; j++) {
2274 if (mesa_instructions[j].Opcode == OPCODE_BRK ||
2275 mesa_instructions[j].Opcode == OPCODE_CONT) {
2276 if (mesa_instructions[j].BranchTarget == -1) {
2277 mesa_instructions[j].BranchTarget = i;
2278 }
2279 }
2280 }
2281 /* The loop ends point at each other. */
2282 mesa_instructions[i].BranchTarget = loop_stack[loop_stack_pos];
2283 mesa_instructions[loop_stack[loop_stack_pos]].BranchTarget = i;
2284 break;
2285 case OPCODE_CAL:
2286 foreach_in_list(function_entry, entry, &v->function_signatures) {
2287 if (entry->sig_id == mesa_instructions[i].BranchTarget) {
2288 mesa_instructions[i].BranchTarget = entry->inst;
2289 break;
2290 }
2291 }
2292 break;
2293 default:
2294 break;
2295 }
2296 }
2297 }
2298
2299 static void
print_program(struct prog_instruction * mesa_instructions,ir_instruction ** mesa_instruction_annotation,int num_instructions)2300 print_program(struct prog_instruction *mesa_instructions,
2301 ir_instruction **mesa_instruction_annotation,
2302 int num_instructions)
2303 {
2304 ir_instruction *last_ir = NULL;
2305 int i;
2306 int indent = 0;
2307
2308 for (i = 0; i < num_instructions; i++) {
2309 struct prog_instruction *mesa_inst = mesa_instructions + i;
2310 ir_instruction *ir = mesa_instruction_annotation[i];
2311
2312 fprintf(stdout, "%3d: ", i);
2313
2314 if (last_ir != ir && ir) {
2315 int j;
2316
2317 for (j = 0; j < indent; j++) {
2318 fprintf(stdout, " ");
2319 }
2320 ir->print();
2321 printf("\n");
2322 last_ir = ir;
2323
2324 fprintf(stdout, " "); /* line number spacing. */
2325 }
2326
2327 indent = _mesa_fprint_instruction_opt(stdout, mesa_inst, indent,
2328 PROG_PRINT_DEBUG, NULL);
2329 }
2330 }
2331
2332 namespace {
2333
2334 class add_uniform_to_shader : public program_resource_visitor {
2335 public:
add_uniform_to_shader(struct gl_context * ctx,struct gl_shader_program * shader_program,struct gl_program_parameter_list * params)2336 add_uniform_to_shader(struct gl_context *ctx,
2337 struct gl_shader_program *shader_program,
2338 struct gl_program_parameter_list *params)
2339 : ctx(ctx), shader_program(shader_program), params(params), idx(-1),
2340 var(NULL)
2341 {
2342 /* empty */
2343 }
2344
process(ir_variable * var)2345 void process(ir_variable *var)
2346 {
2347 this->idx = -1;
2348 this->var = var;
2349 this->program_resource_visitor::process(var,
2350 ctx->Const.UseSTD430AsDefaultPacking);
2351 var->data.param_index = this->idx;
2352 }
2353
2354 private:
2355 virtual void visit_field(const glsl_type *type, const char *name,
2356 bool row_major, const glsl_type *record_type,
2357 const enum glsl_interface_packing packing,
2358 bool last_field);
2359
2360 struct gl_context *ctx;
2361 struct gl_shader_program *shader_program;
2362 struct gl_program_parameter_list *params;
2363 int idx;
2364 ir_variable *var;
2365 };
2366
2367 } /* anonymous namespace */
2368
2369 void
visit_field(const glsl_type * type,const char * name,bool,const glsl_type *,const enum glsl_interface_packing,bool)2370 add_uniform_to_shader::visit_field(const glsl_type *type, const char *name,
2371 bool /* row_major */,
2372 const glsl_type * /* record_type */,
2373 const enum glsl_interface_packing,
2374 bool /* last_field */)
2375 {
2376 /* opaque types don't use storage in the param list unless they are
2377 * bindless samplers or images.
2378 */
2379 if (type->contains_opaque() && !var->data.bindless)
2380 return;
2381
2382 /* Add the uniform to the param list */
2383 assert(_mesa_lookup_parameter_index(params, name) < 0);
2384 int index = _mesa_lookup_parameter_index(params, name);
2385
2386 unsigned num_params = type->arrays_of_arrays_size();
2387 num_params = MAX2(num_params, 1);
2388 num_params *= type->without_array()->matrix_columns;
2389
2390 bool is_dual_slot = type->without_array()->is_dual_slot();
2391 if (is_dual_slot)
2392 num_params *= 2;
2393
2394 _mesa_reserve_parameter_storage(params, num_params);
2395 index = params->NumParameters;
2396
2397 if (ctx->Const.PackedDriverUniformStorage) {
2398 for (unsigned i = 0; i < num_params; i++) {
2399 unsigned dmul = type->without_array()->is_64bit() ? 2 : 1;
2400 unsigned comps = type->without_array()->vector_elements * dmul;
2401 if (is_dual_slot) {
2402 if (i & 0x1)
2403 comps -= 4;
2404 else
2405 comps = 4;
2406 }
2407
2408 _mesa_add_parameter(params, PROGRAM_UNIFORM, name, comps,
2409 type->gl_type, NULL, NULL, false);
2410 }
2411 } else {
2412 for (unsigned i = 0; i < num_params; i++) {
2413 _mesa_add_parameter(params, PROGRAM_UNIFORM, name, 4,
2414 type->gl_type, NULL, NULL, true);
2415 }
2416 }
2417
2418 /* The first part of the uniform that's processed determines the base
2419 * location of the whole uniform (for structures).
2420 */
2421 if (this->idx < 0)
2422 this->idx = index;
2423
2424 /* Each Parameter will hold the index to the backing uniform storage.
2425 * This avoids relying on names to match parameters and uniform
2426 * storages later when associating uniform storage.
2427 */
2428 unsigned location = -1;
2429 ASSERTED const bool found =
2430 shader_program->UniformHash->get(location, params->Parameters[index].Name);
2431 assert(found);
2432
2433 for (unsigned i = 0; i < num_params; i++) {
2434 struct gl_program_parameter *param = ¶ms->Parameters[index + i];
2435 param->UniformStorageIndex = location;
2436 param->MainUniformStorageIndex = params->Parameters[this->idx].UniformStorageIndex;
2437 }
2438 }
2439
2440 /**
2441 * Generate the program parameters list for the user uniforms in a shader
2442 *
2443 * \param shader_program Linked shader program. This is only used to
2444 * emit possible link errors to the info log.
2445 * \param sh Shader whose uniforms are to be processed.
2446 * \param params Parameter list to be filled in.
2447 */
2448 void
_mesa_generate_parameters_list_for_uniforms(struct gl_context * ctx,struct gl_shader_program * shader_program,struct gl_linked_shader * sh,struct gl_program_parameter_list * params)2449 _mesa_generate_parameters_list_for_uniforms(struct gl_context *ctx,
2450 struct gl_shader_program
2451 *shader_program,
2452 struct gl_linked_shader *sh,
2453 struct gl_program_parameter_list
2454 *params)
2455 {
2456 add_uniform_to_shader add(ctx, shader_program, params);
2457
2458 foreach_in_list(ir_instruction, node, sh->ir) {
2459 ir_variable *var = node->as_variable();
2460
2461 if ((var == NULL) || (var->data.mode != ir_var_uniform)
2462 || var->is_in_buffer_block() || (strncmp(var->name, "gl_", 3) == 0))
2463 continue;
2464
2465 add.process(var);
2466 }
2467 }
2468
2469 void
_mesa_associate_uniform_storage(struct gl_context * ctx,struct gl_shader_program * shader_program,struct gl_program * prog)2470 _mesa_associate_uniform_storage(struct gl_context *ctx,
2471 struct gl_shader_program *shader_program,
2472 struct gl_program *prog)
2473 {
2474 struct gl_program_parameter_list *params = prog->Parameters;
2475 gl_shader_stage shader_type = prog->info.stage;
2476
2477 /* After adding each uniform to the parameter list, connect the storage for
2478 * the parameter with the tracking structure used by the API for the
2479 * uniform.
2480 */
2481 unsigned last_location = unsigned(~0);
2482 for (unsigned i = 0; i < params->NumParameters; i++) {
2483 if (params->Parameters[i].Type != PROGRAM_UNIFORM)
2484 continue;
2485
2486 unsigned location = params->Parameters[i].UniformStorageIndex;
2487
2488 struct gl_uniform_storage *storage =
2489 &shader_program->data->UniformStorage[location];
2490
2491 /* Do not associate any uniform storage to built-in uniforms */
2492 if (storage->builtin)
2493 continue;
2494
2495 if (location != last_location) {
2496 enum gl_uniform_driver_format format = uniform_native;
2497 unsigned columns = 0;
2498
2499 int dmul;
2500 if (ctx->Const.PackedDriverUniformStorage && !prog->is_arb_asm) {
2501 dmul = storage->type->vector_elements * sizeof(float);
2502 } else {
2503 dmul = 4 * sizeof(float);
2504 }
2505
2506 switch (storage->type->base_type) {
2507 case GLSL_TYPE_UINT64:
2508 if (storage->type->vector_elements > 2)
2509 dmul *= 2;
2510 /* fallthrough */
2511 case GLSL_TYPE_UINT:
2512 case GLSL_TYPE_UINT16:
2513 case GLSL_TYPE_UINT8:
2514 assert(ctx->Const.NativeIntegers);
2515 format = uniform_native;
2516 columns = 1;
2517 break;
2518 case GLSL_TYPE_INT64:
2519 if (storage->type->vector_elements > 2)
2520 dmul *= 2;
2521 /* fallthrough */
2522 case GLSL_TYPE_INT:
2523 case GLSL_TYPE_INT16:
2524 case GLSL_TYPE_INT8:
2525 format =
2526 (ctx->Const.NativeIntegers) ? uniform_native : uniform_int_float;
2527 columns = 1;
2528 break;
2529 case GLSL_TYPE_DOUBLE:
2530 if (storage->type->vector_elements > 2)
2531 dmul *= 2;
2532 /* fallthrough */
2533 case GLSL_TYPE_FLOAT:
2534 case GLSL_TYPE_FLOAT16:
2535 format = uniform_native;
2536 columns = storage->type->matrix_columns;
2537 break;
2538 case GLSL_TYPE_BOOL:
2539 format = uniform_native;
2540 columns = 1;
2541 break;
2542 case GLSL_TYPE_SAMPLER:
2543 case GLSL_TYPE_IMAGE:
2544 case GLSL_TYPE_SUBROUTINE:
2545 format = uniform_native;
2546 columns = 1;
2547 break;
2548 case GLSL_TYPE_ATOMIC_UINT:
2549 case GLSL_TYPE_ARRAY:
2550 case GLSL_TYPE_VOID:
2551 case GLSL_TYPE_STRUCT:
2552 case GLSL_TYPE_ERROR:
2553 case GLSL_TYPE_INTERFACE:
2554 case GLSL_TYPE_FUNCTION:
2555 assert(!"Should not get here.");
2556 break;
2557 }
2558
2559 unsigned pvo = params->ParameterValueOffset[i];
2560 _mesa_uniform_attach_driver_storage(storage, dmul * columns, dmul,
2561 format,
2562 ¶ms->ParameterValues[pvo]);
2563
2564 /* When a bindless sampler/image is bound to a texture/image unit, we
2565 * have to overwrite the constant value by the resident handle
2566 * directly in the constant buffer before the next draw. One solution
2567 * is to keep track a pointer to the base of the data.
2568 */
2569 if (storage->is_bindless && (prog->sh.NumBindlessSamplers ||
2570 prog->sh.NumBindlessImages)) {
2571 unsigned array_elements = MAX2(1, storage->array_elements);
2572
2573 for (unsigned j = 0; j < array_elements; ++j) {
2574 unsigned unit = storage->opaque[shader_type].index + j;
2575
2576 if (storage->type->without_array()->is_sampler()) {
2577 assert(unit >= 0 && unit < prog->sh.NumBindlessSamplers);
2578 prog->sh.BindlessSamplers[unit].data =
2579 ¶ms->ParameterValues[pvo] + 4 * j;
2580 } else if (storage->type->without_array()->is_image()) {
2581 assert(unit >= 0 && unit < prog->sh.NumBindlessImages);
2582 prog->sh.BindlessImages[unit].data =
2583 ¶ms->ParameterValues[pvo] + 4 * j;
2584 }
2585 }
2586 }
2587
2588 /* After attaching the driver's storage to the uniform, propagate any
2589 * data from the linker's backing store. This will cause values from
2590 * initializers in the source code to be copied over.
2591 */
2592 unsigned array_elements = MAX2(1, storage->array_elements);
2593 if (ctx->Const.PackedDriverUniformStorage && !prog->is_arb_asm &&
2594 (storage->is_bindless || !storage->type->contains_opaque())) {
2595 const int dmul = storage->type->is_64bit() ? 2 : 1;
2596 const unsigned components =
2597 storage->type->vector_elements *
2598 storage->type->matrix_columns;
2599
2600 for (unsigned s = 0; s < storage->num_driver_storage; s++) {
2601 gl_constant_value *uni_storage = (gl_constant_value *)
2602 storage->driver_storage[s].data;
2603 memcpy(uni_storage, storage->storage,
2604 sizeof(storage->storage[0]) * components *
2605 array_elements * dmul);
2606 }
2607 } else {
2608 _mesa_propagate_uniforms_to_driver_storage(storage, 0,
2609 array_elements);
2610 }
2611
2612 last_location = location;
2613 }
2614 }
2615 }
2616
2617 /*
2618 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
2619 * channels for copy propagation and updates following instructions to
2620 * use the original versions.
2621 *
2622 * The ir_to_mesa_visitor lazily produces code assuming that this pass
2623 * will occur. As an example, a TXP production before this pass:
2624 *
2625 * 0: MOV TEMP[1], INPUT[4].xyyy;
2626 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2627 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
2628 *
2629 * and after:
2630 *
2631 * 0: MOV TEMP[1], INPUT[4].xyyy;
2632 * 1: MOV TEMP[1].w, INPUT[4].wwww;
2633 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
2634 *
2635 * which allows for dead code elimination on TEMP[1]'s writes.
2636 */
2637 void
copy_propagate(void)2638 ir_to_mesa_visitor::copy_propagate(void)
2639 {
2640 ir_to_mesa_instruction **acp = rzalloc_array(mem_ctx,
2641 ir_to_mesa_instruction *,
2642 this->next_temp * 4);
2643 int *acp_level = rzalloc_array(mem_ctx, int, this->next_temp * 4);
2644 int level = 0;
2645
2646 foreach_in_list(ir_to_mesa_instruction, inst, &this->instructions) {
2647 assert(inst->dst.file != PROGRAM_TEMPORARY
2648 || inst->dst.index < this->next_temp);
2649
2650 /* First, do any copy propagation possible into the src regs. */
2651 for (int r = 0; r < 3; r++) {
2652 ir_to_mesa_instruction *first = NULL;
2653 bool good = true;
2654 int acp_base = inst->src[r].index * 4;
2655
2656 if (inst->src[r].file != PROGRAM_TEMPORARY ||
2657 inst->src[r].reladdr)
2658 continue;
2659
2660 /* See if we can find entries in the ACP consisting of MOVs
2661 * from the same src register for all the swizzled channels
2662 * of this src register reference.
2663 */
2664 for (int i = 0; i < 4; i++) {
2665 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
2666 ir_to_mesa_instruction *copy_chan = acp[acp_base + src_chan];
2667
2668 if (!copy_chan) {
2669 good = false;
2670 break;
2671 }
2672
2673 assert(acp_level[acp_base + src_chan] <= level);
2674
2675 if (!first) {
2676 first = copy_chan;
2677 } else {
2678 if (first->src[0].file != copy_chan->src[0].file ||
2679 first->src[0].index != copy_chan->src[0].index) {
2680 good = false;
2681 break;
2682 }
2683 }
2684 }
2685
2686 if (good) {
2687 /* We've now validated that we can copy-propagate to
2688 * replace this src register reference. Do it.
2689 */
2690 inst->src[r].file = first->src[0].file;
2691 inst->src[r].index = first->src[0].index;
2692
2693 int swizzle = 0;
2694 for (int i = 0; i < 4; i++) {
2695 int src_chan = GET_SWZ(inst->src[r].swizzle, i);
2696 ir_to_mesa_instruction *copy_inst = acp[acp_base + src_chan];
2697 swizzle |= (GET_SWZ(copy_inst->src[0].swizzle, src_chan) <<
2698 (3 * i));
2699 }
2700 inst->src[r].swizzle = swizzle;
2701 }
2702 }
2703
2704 switch (inst->op) {
2705 case OPCODE_BGNLOOP:
2706 case OPCODE_ENDLOOP:
2707 /* End of a basic block, clear the ACP entirely. */
2708 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
2709 break;
2710
2711 case OPCODE_IF:
2712 ++level;
2713 break;
2714
2715 case OPCODE_ENDIF:
2716 case OPCODE_ELSE:
2717 /* Clear all channels written inside the block from the ACP, but
2718 * leaving those that were not touched.
2719 */
2720 for (int r = 0; r < this->next_temp; r++) {
2721 for (int c = 0; c < 4; c++) {
2722 if (!acp[4 * r + c])
2723 continue;
2724
2725 if (acp_level[4 * r + c] >= level)
2726 acp[4 * r + c] = NULL;
2727 }
2728 }
2729 if (inst->op == OPCODE_ENDIF)
2730 --level;
2731 break;
2732
2733 default:
2734 /* Continuing the block, clear any written channels from
2735 * the ACP.
2736 */
2737 if (inst->dst.file == PROGRAM_TEMPORARY && inst->dst.reladdr) {
2738 /* Any temporary might be written, so no copy propagation
2739 * across this instruction.
2740 */
2741 memset(acp, 0, sizeof(*acp) * this->next_temp * 4);
2742 } else if (inst->dst.file == PROGRAM_OUTPUT &&
2743 inst->dst.reladdr) {
2744 /* Any output might be written, so no copy propagation
2745 * from outputs across this instruction.
2746 */
2747 for (int r = 0; r < this->next_temp; r++) {
2748 for (int c = 0; c < 4; c++) {
2749 if (!acp[4 * r + c])
2750 continue;
2751
2752 if (acp[4 * r + c]->src[0].file == PROGRAM_OUTPUT)
2753 acp[4 * r + c] = NULL;
2754 }
2755 }
2756 } else if (inst->dst.file == PROGRAM_TEMPORARY ||
2757 inst->dst.file == PROGRAM_OUTPUT) {
2758 /* Clear where it's used as dst. */
2759 if (inst->dst.file == PROGRAM_TEMPORARY) {
2760 for (int c = 0; c < 4; c++) {
2761 if (inst->dst.writemask & (1 << c)) {
2762 acp[4 * inst->dst.index + c] = NULL;
2763 }
2764 }
2765 }
2766
2767 /* Clear where it's used as src. */
2768 for (int r = 0; r < this->next_temp; r++) {
2769 for (int c = 0; c < 4; c++) {
2770 if (!acp[4 * r + c])
2771 continue;
2772
2773 int src_chan = GET_SWZ(acp[4 * r + c]->src[0].swizzle, c);
2774
2775 if (acp[4 * r + c]->src[0].file == inst->dst.file &&
2776 acp[4 * r + c]->src[0].index == inst->dst.index &&
2777 inst->dst.writemask & (1 << src_chan))
2778 {
2779 acp[4 * r + c] = NULL;
2780 }
2781 }
2782 }
2783 }
2784 break;
2785 }
2786
2787 /* If this is a copy, add it to the ACP. */
2788 if (inst->op == OPCODE_MOV &&
2789 inst->dst.file == PROGRAM_TEMPORARY &&
2790 !(inst->dst.file == inst->src[0].file &&
2791 inst->dst.index == inst->src[0].index) &&
2792 !inst->dst.reladdr &&
2793 !inst->saturate &&
2794 !inst->src[0].reladdr &&
2795 !inst->src[0].negate) {
2796 for (int i = 0; i < 4; i++) {
2797 if (inst->dst.writemask & (1 << i)) {
2798 acp[4 * inst->dst.index + i] = inst;
2799 acp_level[4 * inst->dst.index + i] = level;
2800 }
2801 }
2802 }
2803 }
2804
2805 ralloc_free(acp_level);
2806 ralloc_free(acp);
2807 }
2808
2809
2810 /**
2811 * Convert a shader's GLSL IR into a Mesa gl_program.
2812 */
2813 static struct gl_program *
get_mesa_program(struct gl_context * ctx,struct gl_shader_program * shader_program,struct gl_linked_shader * shader)2814 get_mesa_program(struct gl_context *ctx,
2815 struct gl_shader_program *shader_program,
2816 struct gl_linked_shader *shader)
2817 {
2818 ir_to_mesa_visitor v;
2819 struct prog_instruction *mesa_instructions, *mesa_inst;
2820 ir_instruction **mesa_instruction_annotation;
2821 int i;
2822 struct gl_program *prog;
2823 GLenum target = _mesa_shader_stage_to_program(shader->Stage);
2824 const char *target_string = _mesa_shader_stage_to_string(shader->Stage);
2825 struct gl_shader_compiler_options *options =
2826 &ctx->Const.ShaderCompilerOptions[shader->Stage];
2827
2828 validate_ir_tree(shader->ir);
2829
2830 prog = shader->Program;
2831 prog->Parameters = _mesa_new_parameter_list();
2832 v.ctx = ctx;
2833 v.prog = prog;
2834 v.shader_program = shader_program;
2835 v.options = options;
2836
2837 _mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader,
2838 prog->Parameters);
2839
2840 /* Emit Mesa IR for main(). */
2841 visit_exec_list(shader->ir, &v);
2842 v.emit(NULL, OPCODE_END);
2843
2844 prog->arb.NumTemporaries = v.next_temp;
2845
2846 unsigned num_instructions = v.instructions.length();
2847
2848 mesa_instructions = rzalloc_array(prog, struct prog_instruction,
2849 num_instructions);
2850 mesa_instruction_annotation = ralloc_array(v.mem_ctx, ir_instruction *,
2851 num_instructions);
2852
2853 v.copy_propagate();
2854
2855 /* Convert ir_mesa_instructions into prog_instructions.
2856 */
2857 mesa_inst = mesa_instructions;
2858 i = 0;
2859 foreach_in_list(const ir_to_mesa_instruction, inst, &v.instructions) {
2860 mesa_inst->Opcode = inst->op;
2861 if (inst->saturate)
2862 mesa_inst->Saturate = GL_TRUE;
2863 mesa_inst->DstReg.File = inst->dst.file;
2864 mesa_inst->DstReg.Index = inst->dst.index;
2865 mesa_inst->DstReg.WriteMask = inst->dst.writemask;
2866 mesa_inst->DstReg.RelAddr = inst->dst.reladdr != NULL;
2867 mesa_inst->SrcReg[0] = mesa_src_reg_from_ir_src_reg(inst->src[0]);
2868 mesa_inst->SrcReg[1] = mesa_src_reg_from_ir_src_reg(inst->src[1]);
2869 mesa_inst->SrcReg[2] = mesa_src_reg_from_ir_src_reg(inst->src[2]);
2870 mesa_inst->TexSrcUnit = inst->sampler;
2871 mesa_inst->TexSrcTarget = inst->tex_target;
2872 mesa_inst->TexShadow = inst->tex_shadow;
2873 mesa_instruction_annotation[i] = inst->ir;
2874
2875 /* Set IndirectRegisterFiles. */
2876 if (mesa_inst->DstReg.RelAddr)
2877 prog->arb.IndirectRegisterFiles |= 1 << mesa_inst->DstReg.File;
2878
2879 /* Update program's bitmask of indirectly accessed register files */
2880 for (unsigned src = 0; src < 3; src++)
2881 if (mesa_inst->SrcReg[src].RelAddr)
2882 prog->arb.IndirectRegisterFiles |= 1 << mesa_inst->SrcReg[src].File;
2883
2884 switch (mesa_inst->Opcode) {
2885 case OPCODE_IF:
2886 if (options->MaxIfDepth == 0) {
2887 linker_warning(shader_program,
2888 "Couldn't flatten if-statement. "
2889 "This will likely result in software "
2890 "rasterization.\n");
2891 }
2892 break;
2893 case OPCODE_BGNLOOP:
2894 if (options->EmitNoLoops) {
2895 linker_warning(shader_program,
2896 "Couldn't unroll loop. "
2897 "This will likely result in software "
2898 "rasterization.\n");
2899 }
2900 break;
2901 case OPCODE_CONT:
2902 if (options->EmitNoCont) {
2903 linker_warning(shader_program,
2904 "Couldn't lower continue-statement. "
2905 "This will likely result in software "
2906 "rasterization.\n");
2907 }
2908 break;
2909 case OPCODE_ARL:
2910 prog->arb.NumAddressRegs = 1;
2911 break;
2912 default:
2913 break;
2914 }
2915
2916 mesa_inst++;
2917 i++;
2918
2919 if (!shader_program->data->LinkStatus)
2920 break;
2921 }
2922
2923 if (!shader_program->data->LinkStatus) {
2924 goto fail_exit;
2925 }
2926
2927 set_branchtargets(&v, mesa_instructions, num_instructions);
2928
2929 if (ctx->_Shader->Flags & GLSL_DUMP) {
2930 fprintf(stderr, "\n");
2931 fprintf(stderr, "GLSL IR for linked %s program %d:\n", target_string,
2932 shader_program->Name);
2933 _mesa_print_ir(stderr, shader->ir, NULL);
2934 fprintf(stderr, "\n");
2935 fprintf(stderr, "\n");
2936 fprintf(stderr, "Mesa IR for linked %s program %d:\n", target_string,
2937 shader_program->Name);
2938 print_program(mesa_instructions, mesa_instruction_annotation,
2939 num_instructions);
2940 fflush(stderr);
2941 }
2942
2943 prog->arb.Instructions = mesa_instructions;
2944 prog->arb.NumInstructions = num_instructions;
2945
2946 /* Setting this to NULL prevents a possible double free in the fail_exit
2947 * path (far below).
2948 */
2949 mesa_instructions = NULL;
2950
2951 do_set_program_inouts(shader->ir, prog, shader->Stage);
2952
2953 prog->ShadowSamplers = shader->shadow_samplers;
2954 prog->ExternalSamplersUsed = gl_external_samplers(prog);
2955 _mesa_update_shader_textures_used(shader_program, prog);
2956
2957 /* Set the gl_FragDepth layout. */
2958 if (target == GL_FRAGMENT_PROGRAM_ARB) {
2959 prog->info.fs.depth_layout = shader_program->FragDepthLayout;
2960 }
2961
2962 _mesa_optimize_program(prog, prog);
2963
2964 /* This has to be done last. Any operation that can cause
2965 * prog->ParameterValues to get reallocated (e.g., anything that adds a
2966 * program constant) has to happen before creating this linkage.
2967 */
2968 _mesa_associate_uniform_storage(ctx, shader_program, prog);
2969 if (!shader_program->data->LinkStatus) {
2970 goto fail_exit;
2971 }
2972
2973 return prog;
2974
2975 fail_exit:
2976 ralloc_free(mesa_instructions);
2977 _mesa_reference_program(ctx, &shader->Program, NULL);
2978 return NULL;
2979 }
2980
2981 extern "C" {
2982
2983 /**
2984 * Link a shader.
2985 * Called via ctx->Driver.LinkShader()
2986 * This actually involves converting GLSL IR into Mesa gl_programs with
2987 * code lowering and other optimizations.
2988 */
2989 GLboolean
_mesa_ir_link_shader(struct gl_context * ctx,struct gl_shader_program * prog)2990 _mesa_ir_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
2991 {
2992 assert(prog->data->LinkStatus);
2993
2994 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2995 if (prog->_LinkedShaders[i] == NULL)
2996 continue;
2997
2998 bool progress;
2999 exec_list *ir = prog->_LinkedShaders[i]->ir;
3000 const struct gl_shader_compiler_options *options =
3001 &ctx->Const.ShaderCompilerOptions[prog->_LinkedShaders[i]->Stage];
3002
3003 do {
3004 progress = false;
3005
3006 /* Lowering */
3007 do_mat_op_to_vec(ir);
3008 lower_instructions(ir, (MOD_TO_FLOOR | DIV_TO_MUL_RCP | EXP_TO_EXP2
3009 | LOG_TO_LOG2 | INT_DIV_TO_MUL_RCP
3010 | MUL64_TO_MUL_AND_MUL_HIGH
3011 | ((options->EmitNoPow) ? POW_TO_EXP2 : 0)));
3012
3013 progress = do_common_optimization(ir, true, true,
3014 options, ctx->Const.NativeIntegers)
3015 || progress;
3016
3017 progress = lower_quadop_vector(ir, true) || progress;
3018
3019 if (options->MaxIfDepth == 0)
3020 progress = lower_discard(ir) || progress;
3021
3022 progress = lower_if_to_cond_assign((gl_shader_stage)i, ir,
3023 options->MaxIfDepth) || progress;
3024
3025 /* If there are forms of indirect addressing that the driver
3026 * cannot handle, perform the lowering pass.
3027 */
3028 if (options->EmitNoIndirectInput || options->EmitNoIndirectOutput
3029 || options->EmitNoIndirectTemp || options->EmitNoIndirectUniform)
3030 progress =
3031 lower_variable_index_to_cond_assign(prog->_LinkedShaders[i]->Stage, ir,
3032 options->EmitNoIndirectInput,
3033 options->EmitNoIndirectOutput,
3034 options->EmitNoIndirectTemp,
3035 options->EmitNoIndirectUniform)
3036 || progress;
3037
3038 progress = do_vec_index_to_cond_assign(ir) || progress;
3039 progress = lower_vector_insert(ir, true) || progress;
3040 } while (progress);
3041
3042 validate_ir_tree(ir);
3043 }
3044
3045 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3046 struct gl_program *linked_prog;
3047
3048 if (prog->_LinkedShaders[i] == NULL)
3049 continue;
3050
3051 linked_prog = get_mesa_program(ctx, prog, prog->_LinkedShaders[i]);
3052
3053 if (linked_prog) {
3054 _mesa_copy_linked_program_data(prog, prog->_LinkedShaders[i]);
3055
3056 if (!ctx->Driver.ProgramStringNotify(ctx,
3057 _mesa_shader_stage_to_program(i),
3058 linked_prog)) {
3059 _mesa_reference_program(ctx, &prog->_LinkedShaders[i]->Program,
3060 NULL);
3061 return GL_FALSE;
3062 }
3063 }
3064 }
3065
3066 build_program_resource_list(ctx, prog, false);
3067 return prog->data->LinkStatus;
3068 }
3069
3070 /**
3071 * Link a GLSL shader program. Called via glLinkProgram().
3072 */
3073 void
_mesa_glsl_link_shader(struct gl_context * ctx,struct gl_shader_program * prog)3074 _mesa_glsl_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
3075 {
3076 unsigned int i;
3077 bool spirv = false;
3078
3079 _mesa_clear_shader_program_data(ctx, prog);
3080
3081 prog->data = _mesa_create_shader_program_data();
3082
3083 prog->data->LinkStatus = LINKING_SUCCESS;
3084
3085 for (i = 0; i < prog->NumShaders; i++) {
3086 if (!prog->Shaders[i]->CompileStatus) {
3087 linker_error(prog, "linking with uncompiled/unspecialized shader");
3088 }
3089
3090 if (!i) {
3091 spirv = (prog->Shaders[i]->spirv_data != NULL);
3092 } else if (spirv && !prog->Shaders[i]->spirv_data) {
3093 /* The GL_ARB_gl_spirv spec adds a new bullet point to the list of
3094 * reasons LinkProgram can fail:
3095 *
3096 * "All the shader objects attached to <program> do not have the
3097 * same value for the SPIR_V_BINARY_ARB state."
3098 */
3099 linker_error(prog,
3100 "not all attached shaders have the same "
3101 "SPIR_V_BINARY_ARB state");
3102 }
3103 }
3104 prog->data->spirv = spirv;
3105
3106 if (prog->data->LinkStatus) {
3107 if (!spirv)
3108 link_shaders(ctx, prog);
3109 else
3110 _mesa_spirv_link_shaders(ctx, prog);
3111 }
3112
3113 /* If LinkStatus is LINKING_SUCCESS, then reset sampler validated to true.
3114 * Validation happens via the LinkShader call below. If LinkStatus is
3115 * LINKING_SKIPPED, then SamplersValidated will have been restored from the
3116 * shader cache.
3117 */
3118 if (prog->data->LinkStatus == LINKING_SUCCESS) {
3119 prog->SamplersValidated = GL_TRUE;
3120 }
3121
3122 if (prog->data->LinkStatus && !ctx->Driver.LinkShader(ctx, prog)) {
3123 prog->data->LinkStatus = LINKING_FAILURE;
3124 }
3125
3126 if (prog->data->LinkStatus != LINKING_FAILURE)
3127 _mesa_create_program_resource_hash(prog);
3128
3129 /* Return early if we are loading the shader from on-disk cache */
3130 if (prog->data->LinkStatus == LINKING_SKIPPED)
3131 return;
3132
3133 if (ctx->_Shader->Flags & GLSL_DUMP) {
3134 if (!prog->data->LinkStatus) {
3135 fprintf(stderr, "GLSL shader program %d failed to link\n", prog->Name);
3136 }
3137
3138 if (prog->data->InfoLog && prog->data->InfoLog[0] != 0) {
3139 fprintf(stderr, "GLSL shader program %d info log:\n", prog->Name);
3140 fprintf(stderr, "%s\n", prog->data->InfoLog);
3141 }
3142 }
3143
3144 #ifdef ENABLE_SHADER_CACHE
3145 if (prog->data->LinkStatus)
3146 shader_cache_write_program_metadata(ctx, prog);
3147 #endif
3148 }
3149
3150 } /* extern "C" */
3151