1/* 2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a55.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A55 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19 /* -------------------------------------------------- 20 * Errata Workaround for Cortex A55 Errata #768277. 21 * This applies only to revision r0p0 of Cortex A55. 22 * Inputs: 23 * x0: variant[4:7] and revision[0:3] of current cpu. 24 * Shall clobber: x0-x17 25 * -------------------------------------------------- 26 */ 27func errata_a55_768277_wa 28 /* 29 * Compare x0 against revision r0p0 30 */ 31 mov x17, x30 32 bl check_errata_768277 33 cbz x0, 1f 34 mrs x1, CORTEX_A55_CPUACTLR_EL1 35 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE 36 msr CORTEX_A55_CPUACTLR_EL1, x1 37 isb 381: 39 ret x17 40endfunc errata_a55_768277_wa 41 42func check_errata_768277 43 mov x1, #0x00 44 b cpu_rev_var_ls 45endfunc check_errata_768277 46 47 /* ------------------------------------------------------------------ 48 * Errata Workaround for Cortex A55 Errata #778703. 49 * This applies only to revision r0p0 of Cortex A55 where L2 cache is 50 * not configured. 51 * Inputs: 52 * x0: variant[4:7] and revision[0:3] of current cpu. 53 * Shall clobber: x0-x17 54 * ------------------------------------------------------------------ 55 */ 56func errata_a55_778703_wa 57 /* 58 * Compare x0 against revision r0p0 and check that no private L2 cache 59 * is configured 60 */ 61 mov x17, x30 62 bl check_errata_778703 63 cbz x0, 1f 64 mrs x1, CORTEX_A55_CPUECTLR_EL1 65 orr x1, x1, #CORTEX_A55_CPUECTLR_EL1_L1WSCTL 66 msr CORTEX_A55_CPUECTLR_EL1, x1 67 mrs x1, CORTEX_A55_CPUACTLR_EL1 68 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING 69 msr CORTEX_A55_CPUACTLR_EL1, x1 70 isb 711: 72 ret x17 73endfunc errata_a55_778703_wa 74 75func check_errata_778703 76 mov x16, x30 77 mov x1, #0x00 78 bl cpu_rev_var_ls 79 /* 80 * Check that no private L2 cache is configured 81 */ 82 mrs x1, CORTEX_A55_CLIDR_EL1 83 and x1, x1, CORTEX_A55_CLIDR_EL1_CTYPE3 84 cmp x1, #0 85 mov x2, #ERRATA_NOT_APPLIES 86 csel x0, x0, x2, eq 87 ret x16 88endfunc check_errata_778703 89 90 /* -------------------------------------------------- 91 * Errata Workaround for Cortex A55 Errata #798797. 92 * This applies only to revision r0p0 of Cortex A55. 93 * Inputs: 94 * x0: variant[4:7] and revision[0:3] of current cpu. 95 * Shall clobber: x0-x17 96 * -------------------------------------------------- 97 */ 98func errata_a55_798797_wa 99 /* 100 * Compare x0 against revision r0p0 101 */ 102 mov x17, x30 103 bl check_errata_798797 104 cbz x0, 1f 105 mrs x1, CORTEX_A55_CPUACTLR_EL1 106 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS 107 msr CORTEX_A55_CPUACTLR_EL1, x1 108 isb 1091: 110 ret x17 111endfunc errata_a55_798797_wa 112 113func check_errata_798797 114 mov x1, #0x00 115 b cpu_rev_var_ls 116endfunc check_errata_798797 117 118 /* -------------------------------------------------------------------- 119 * Errata Workaround for Cortex A55 Errata #846532. 120 * This applies only to revisions <= r0p1 of Cortex A55. 121 * Disabling dual-issue has a small impact on performance. Disabling a 122 * power optimization feature is an alternate workaround with no impact 123 * on performance but with an increase in power consumption (see errata 124 * notice). 125 * Inputs: 126 * x0: variant[4:7] and revision[0:3] of current cpu. 127 * Shall clobber: x0-x17 128 * -------------------------------------------------------------------- 129 */ 130func errata_a55_846532_wa 131 /* 132 * Compare x0 against revision r0p1 133 */ 134 mov x17, x30 135 bl check_errata_846532 136 cbz x0, 1f 137 mrs x1, CORTEX_A55_CPUACTLR_EL1 138 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE 139 msr CORTEX_A55_CPUACTLR_EL1, x1 140 isb 1411: 142 ret x17 143endfunc errata_a55_846532_wa 144 145func check_errata_846532 146 mov x1, #0x01 147 b cpu_rev_var_ls 148endfunc check_errata_846532 149 150 /* ----------------------------------------------------- 151 * Errata Workaround for Cortex A55 Errata #903758. 152 * This applies only to revisions <= r0p1 of Cortex A55. 153 * Inputs: 154 * x0: variant[4:7] and revision[0:3] of current cpu. 155 * Shall clobber: x0-x17 156 * ----------------------------------------------------- 157 */ 158func errata_a55_903758_wa 159 /* 160 * Compare x0 against revision r0p1 161 */ 162 mov x17, x30 163 bl check_errata_903758 164 cbz x0, 1f 165 mrs x1, CORTEX_A55_CPUACTLR_EL1 166 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS 167 msr CORTEX_A55_CPUACTLR_EL1, x1 168 isb 1691: 170 ret x17 171endfunc errata_a55_903758_wa 172 173func check_errata_903758 174 mov x1, #0x01 175 b cpu_rev_var_ls 176endfunc check_errata_903758 177 178 /* ----------------------------------------------------- 179 * Errata Workaround for Cortex A55 Errata #1221012. 180 * This applies only to revisions <= r1p0 of Cortex A55. 181 * Inputs: 182 * x0: variant[4:7] and revision[0:3] of current cpu. 183 * Shall clobber: x0-x17 184 * ----------------------------------------------------- 185 */ 186func errata_a55_1221012_wa 187 /* 188 * Compare x0 against revision r1p0 189 */ 190 mov x17, x30 191 bl check_errata_1221012 192 cbz x0, 1f 193 mov x0, #0x0020 194 movk x0, #0x0850, lsl #16 195 msr CPUPOR_EL3, x0 196 mov x0, #0x0000 197 movk x0, #0x1FF0, lsl #16 198 movk x0, #0x2, lsl #32 199 msr CPUPMR_EL3, x0 200 mov x0, #0x03fd 201 movk x0, #0x0110, lsl #16 202 msr CPUPCR_EL3, x0 203 mov x0, #0x1 204 msr CPUPSELR_EL3, x0 205 mov x0, #0x0040 206 movk x0, #0x08D0, lsl #16 207 msr CPUPOR_EL3, x0 208 mov x0, #0x0040 209 movk x0, #0x1FF0, lsl #16 210 movk x0, #0x2, lsl #32 211 msr CPUPMR_EL3, x0 212 mov x0, #0x03fd 213 movk x0, #0x0110, lsl #16 214 msr CPUPCR_EL3, x0 215 isb 2161: 217 ret x17 218endfunc errata_a55_1221012_wa 219 220func check_errata_1221012 221 mov x1, #0x10 222 b cpu_rev_var_ls 223endfunc check_errata_1221012 224 225 /* -------------------------------------------------- 226 * Errata workaround for Cortex A55 Errata #1530923. 227 * This applies to all revisions of Cortex A55. 228 * -------------------------------------------------- 229 */ 230func check_errata_1530923 231#if ERRATA_A55_1530923 232 mov x0, #ERRATA_APPLIES 233#else 234 mov x0, #ERRATA_MISSING 235#endif 236 ret 237endfunc check_errata_1530923 238 239func cortex_a55_reset_func 240 mov x19, x30 241 242#if ERRATA_DSU_798953 243 bl errata_dsu_798953_wa 244#endif 245 246#if ERRATA_DSU_936184 247 bl errata_dsu_936184_wa 248#endif 249 250 bl cpu_get_rev_var 251 mov x18, x0 252 253#if ERRATA_A55_768277 254 mov x0, x18 255 bl errata_a55_768277_wa 256#endif 257 258#if ERRATA_A55_778703 259 mov x0, x18 260 bl errata_a55_778703_wa 261#endif 262 263#if ERRATA_A55_798797 264 mov x0, x18 265 bl errata_a55_798797_wa 266#endif 267 268#if ERRATA_A55_846532 269 mov x0, x18 270 bl errata_a55_846532_wa 271#endif 272 273#if ERRATA_A55_903758 274 mov x0, x18 275 bl errata_a55_903758_wa 276#endif 277 278#if ERRATA_A55_1221012 279 mov x0, x18 280 bl errata_a55_1221012_wa 281#endif 282 283 ret x19 284endfunc cortex_a55_reset_func 285 286 /* --------------------------------------------- 287 * HW will do the cache maintenance while powering down 288 * --------------------------------------------- 289 */ 290func cortex_a55_core_pwr_dwn 291 /* --------------------------------------------- 292 * Enable CPU power down bit in power control register 293 * --------------------------------------------- 294 */ 295 mrs x0, CORTEX_A55_CPUPWRCTLR_EL1 296 orr x0, x0, #CORTEX_A55_CORE_PWRDN_EN_MASK 297 msr CORTEX_A55_CPUPWRCTLR_EL1, x0 298 isb 299 ret 300endfunc cortex_a55_core_pwr_dwn 301 302#if REPORT_ERRATA 303/* 304 * Errata printing function for Cortex A55. Must follow AAPCS & can use stack. 305 */ 306func cortex_a55_errata_report 307 stp x8, x30, [sp, #-16]! 308 bl cpu_get_rev_var 309 mov x8, x0 310 311 /* 312 * Report all errata. The revision variant information is at x8, where 313 * "report_errata" is expecting it and it doesn't corrupt it. 314 */ 315 report_errata ERRATA_DSU_798953, cortex_a55, dsu_798953 316 report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184 317 report_errata ERRATA_A55_768277, cortex_a55, 768277 318 report_errata ERRATA_A55_778703, cortex_a55, 778703 319 report_errata ERRATA_A55_798797, cortex_a55, 798797 320 report_errata ERRATA_A55_846532, cortex_a55, 846532 321 report_errata ERRATA_A55_903758, cortex_a55, 903758 322 report_errata ERRATA_A55_1221012, cortex_a55, 1221012 323 report_errata ERRATA_A55_1530923, cortex_a55, 1530923 324 325 ldp x8, x30, [sp], #16 326 ret 327endfunc cortex_a55_errata_report 328#endif 329 330 /* --------------------------------------------- 331 * This function provides cortex_a55 specific 332 * register information for crash reporting. 333 * It needs to return with x6 pointing to 334 * a list of register names in ascii and 335 * x8 - x15 having values of registers to be 336 * reported. 337 * --------------------------------------------- 338 */ 339.section .rodata.cortex_a55_regs, "aS" 340cortex_a55_regs: /* The ascii list of register names to be reported */ 341 .asciz "cpuectlr_el1", "" 342 343func cortex_a55_cpu_reg_dump 344 adr x6, cortex_a55_regs 345 mrs x8, CORTEX_A55_CPUECTLR_EL1 346 ret 347endfunc cortex_a55_cpu_reg_dump 348 349declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \ 350 cortex_a55_reset_func, \ 351 cortex_a55_core_pwr_dwn 352