1/* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <common/debug.h> 10#include <neoverse_e1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* ------------------------------------------------- 25 * The CPU Ops reset function for Neoverse-E1. 26 * Shall clobber: x0-x19 27 * ------------------------------------------------- 28 */ 29func neoverse_e1_reset_func 30 mov x19, x30 31 32#if ERRATA_DSU_936184 33 bl errata_dsu_936184_wa 34#endif 35 36 ret x19 37endfunc neoverse_e1_reset_func 38 39func neoverse_e1_cpu_pwr_dwn 40 mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1 41 orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 42 msr NEOVERSE_E1_CPUPWRCTLR_EL1, x0 43 isb 44 ret 45endfunc neoverse_e1_cpu_pwr_dwn 46 47#if REPORT_ERRATA 48/* 49 * Errata printing function for Neoverse N1. Must follow AAPCS. 50 */ 51func neoverse_e1_errata_report 52 stp x8, x30, [sp, #-16]! 53 54 bl cpu_get_rev_var 55 mov x8, x0 56 57 /* 58 * Report all errata. The revision-variant information is passed to 59 * checking functions of each errata. 60 */ 61 report_errata ERRATA_DSU_936184, neoverse_e1, dsu_936184 62 63 ldp x8, x30, [sp], #16 64 ret 65endfunc neoverse_e1_errata_report 66#endif 67 68 69.section .rodata.neoverse_e1_regs, "aS" 70neoverse_e1_regs: /* The ascii list of register names to be reported */ 71 .asciz "cpuectlr_el1", "" 72 73func neoverse_e1_cpu_reg_dump 74 adr x6, neoverse_e1_regs 75 mrs x8, NEOVERSE_E1_ECTLR_EL1 76 ret 77endfunc neoverse_e1_cpu_reg_dump 78 79declare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \ 80 neoverse_e1_reset_func, \ 81 neoverse_e1_cpu_pwr_dwn 82