1/* 2 * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpuamu.h> 10#include <cpu_macros.S> 11#include <context.h> 12#include <neoverse_n1.h> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 .global neoverse_n1_errata_ic_trap_handler 25 26/* -------------------------------------------------- 27 * Errata Workaround for Neoverse N1 Erratum 1043202. 28 * This applies to revision r0p0 and r1p0 of Neoverse N1. 29 * Inputs: 30 * x0: variant[4:7] and revision[0:3] of current cpu. 31 * Shall clobber: x0-x17 32 * -------------------------------------------------- 33 */ 34func errata_n1_1043202_wa 35 /* Compare x0 against revision r1p0 */ 36 mov x17, x30 37 bl check_errata_1043202 38 cbz x0, 1f 39 40 /* Apply instruction patching sequence */ 41 ldr x0, =0x0 42 msr CPUPSELR_EL3, x0 43 ldr x0, =0xF3BF8F2F 44 msr CPUPOR_EL3, x0 45 ldr x0, =0xFFFFFFFF 46 msr CPUPMR_EL3, x0 47 ldr x0, =0x800200071 48 msr CPUPCR_EL3, x0 49 isb 501: 51 ret x17 52endfunc errata_n1_1043202_wa 53 54func check_errata_1043202 55 /* Applies to r0p0 and r1p0 */ 56 mov x1, #0x10 57 b cpu_rev_var_ls 58endfunc check_errata_1043202 59 60/* -------------------------------------------------- 61 * Disable speculative loads if Neoverse N1 supports 62 * SSBS. 63 * 64 * Shall clobber: x0. 65 * -------------------------------------------------- 66 */ 67func neoverse_n1_disable_speculative_loads 68 /* Check if the PE implements SSBS */ 69 mrs x0, id_aa64pfr1_el1 70 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 71 b.eq 1f 72 73 /* Disable speculative loads */ 74 msr SSBS, xzr 75 761: 77 ret 78endfunc neoverse_n1_disable_speculative_loads 79 80/* -------------------------------------------------- 81 * Errata Workaround for Neoverse N1 Errata #1073348 82 * This applies to revision r0p0 and r1p0 of Neoverse N1. 83 * Inputs: 84 * x0: variant[4:7] and revision[0:3] of current cpu. 85 * Shall clobber: x0-x17 86 * -------------------------------------------------- 87 */ 88func errata_n1_1073348_wa 89 /* Compare x0 against revision r1p0 */ 90 mov x17, x30 91 bl check_errata_1073348 92 cbz x0, 1f 93 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 94 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 95 msr NEOVERSE_N1_CPUACTLR_EL1, x1 961: 97 ret x17 98endfunc errata_n1_1073348_wa 99 100func check_errata_1073348 101 /* Applies to r0p0 and r1p0 */ 102 mov x1, #0x10 103 b cpu_rev_var_ls 104endfunc check_errata_1073348 105 106/* -------------------------------------------------- 107 * Errata Workaround for Neoverse N1 Errata #1130799 108 * This applies to revision <=r2p0 of Neoverse N1. 109 * Inputs: 110 * x0: variant[4:7] and revision[0:3] of current cpu. 111 * Shall clobber: x0-x17 112 * -------------------------------------------------- 113 */ 114func errata_n1_1130799_wa 115 /* Compare x0 against revision r2p0 */ 116 mov x17, x30 117 bl check_errata_1130799 118 cbz x0, 1f 119 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 120 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 121 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 1221: 123 ret x17 124endfunc errata_n1_1130799_wa 125 126func check_errata_1130799 127 /* Applies to <=r2p0 */ 128 mov x1, #0x20 129 b cpu_rev_var_ls 130endfunc check_errata_1130799 131 132/* -------------------------------------------------- 133 * Errata Workaround for Neoverse N1 Errata #1165347 134 * This applies to revision <=r2p0 of Neoverse N1. 135 * Inputs: 136 * x0: variant[4:7] and revision[0:3] of current cpu. 137 * Shall clobber: x0-x17 138 * -------------------------------------------------- 139 */ 140func errata_n1_1165347_wa 141 /* Compare x0 against revision r2p0 */ 142 mov x17, x30 143 bl check_errata_1165347 144 cbz x0, 1f 145 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 146 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 147 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 148 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 1491: 150 ret x17 151endfunc errata_n1_1165347_wa 152 153func check_errata_1165347 154 /* Applies to <=r2p0 */ 155 mov x1, #0x20 156 b cpu_rev_var_ls 157endfunc check_errata_1165347 158 159/* -------------------------------------------------- 160 * Errata Workaround for Neoverse N1 Errata #1207823 161 * This applies to revision <=r2p0 of Neoverse N1. 162 * Inputs: 163 * x0: variant[4:7] and revision[0:3] of current cpu. 164 * Shall clobber: x0-x17 165 * -------------------------------------------------- 166 */ 167func errata_n1_1207823_wa 168 /* Compare x0 against revision r2p0 */ 169 mov x17, x30 170 bl check_errata_1207823 171 cbz x0, 1f 172 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 173 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 174 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 1751: 176 ret x17 177endfunc errata_n1_1207823_wa 178 179func check_errata_1207823 180 /* Applies to <=r2p0 */ 181 mov x1, #0x20 182 b cpu_rev_var_ls 183endfunc check_errata_1207823 184 185/* -------------------------------------------------- 186 * Errata Workaround for Neoverse N1 Errata #1220197 187 * This applies to revision <=r2p0 of Neoverse N1. 188 * Inputs: 189 * x0: variant[4:7] and revision[0:3] of current cpu. 190 * Shall clobber: x0-x17 191 * -------------------------------------------------- 192 */ 193func errata_n1_1220197_wa 194 /* Compare x0 against revision r2p0 */ 195 mov x17, x30 196 bl check_errata_1220197 197 cbz x0, 1f 198 mrs x1, NEOVERSE_N1_CPUECTLR_EL1 199 orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK 200 msr NEOVERSE_N1_CPUECTLR_EL1, x1 2011: 202 ret x17 203endfunc errata_n1_1220197_wa 204 205func check_errata_1220197 206 /* Applies to <=r2p0 */ 207 mov x1, #0x20 208 b cpu_rev_var_ls 209endfunc check_errata_1220197 210 211/* -------------------------------------------------- 212 * Errata Workaround for Neoverse N1 Errata #1257314 213 * This applies to revision <=r3p0 of Neoverse N1. 214 * Inputs: 215 * x0: variant[4:7] and revision[0:3] of current cpu. 216 * Shall clobber: x0-x17 217 * -------------------------------------------------- 218 */ 219func errata_n1_1257314_wa 220 /* Compare x0 against revision r3p0 */ 221 mov x17, x30 222 bl check_errata_1257314 223 cbz x0, 1f 224 mrs x1, NEOVERSE_N1_CPUACTLR3_EL1 225 orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 226 msr NEOVERSE_N1_CPUACTLR3_EL1, x1 2271: 228 ret x17 229endfunc errata_n1_1257314_wa 230 231func check_errata_1257314 232 /* Applies to <=r3p0 */ 233 mov x1, #0x30 234 b cpu_rev_var_ls 235endfunc check_errata_1257314 236 237/* -------------------------------------------------- 238 * Errata Workaround for Neoverse N1 Errata #1262606 239 * This applies to revision <=r3p0 of Neoverse N1. 240 * Inputs: 241 * x0: variant[4:7] and revision[0:3] of current cpu. 242 * Shall clobber: x0-x17 243 * -------------------------------------------------- 244 */ 245func errata_n1_1262606_wa 246 /* Compare x0 against revision r3p0 */ 247 mov x17, x30 248 bl check_errata_1262606 249 cbz x0, 1f 250 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 251 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 252 msr NEOVERSE_N1_CPUACTLR_EL1, x1 2531: 254 ret x17 255endfunc errata_n1_1262606_wa 256 257func check_errata_1262606 258 /* Applies to <=r3p0 */ 259 mov x1, #0x30 260 b cpu_rev_var_ls 261endfunc check_errata_1262606 262 263/* -------------------------------------------------- 264 * Errata Workaround for Neoverse N1 Errata #1262888 265 * This applies to revision <=r3p0 of Neoverse N1. 266 * Inputs: 267 * x0: variant[4:7] and revision[0:3] of current cpu. 268 * Shall clobber: x0-x17 269 * -------------------------------------------------- 270 */ 271func errata_n1_1262888_wa 272 /* Compare x0 against revision r3p0 */ 273 mov x17, x30 274 bl check_errata_1262888 275 cbz x0, 1f 276 mrs x1, NEOVERSE_N1_CPUECTLR_EL1 277 orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT 278 msr NEOVERSE_N1_CPUECTLR_EL1, x1 2791: 280 ret x17 281endfunc errata_n1_1262888_wa 282 283func check_errata_1262888 284 /* Applies to <=r3p0 */ 285 mov x1, #0x30 286 b cpu_rev_var_ls 287endfunc check_errata_1262888 288 289/* -------------------------------------------------- 290 * Errata Workaround for Neoverse N1 Errata #1275112 291 * This applies to revision <=r3p0 of Neoverse N1. 292 * Inputs: 293 * x0: variant[4:7] and revision[0:3] of current cpu. 294 * Shall clobber: x0-x17 295 * -------------------------------------------------- 296 */ 297func errata_n1_1275112_wa 298 /* Compare x0 against revision r3p0 */ 299 mov x17, x30 300 bl check_errata_1275112 301 cbz x0, 1f 302 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 303 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 304 msr NEOVERSE_N1_CPUACTLR_EL1, x1 3051: 306 ret x17 307endfunc errata_n1_1275112_wa 308 309func check_errata_1275112 310 /* Applies to <=r3p0 */ 311 mov x1, #0x30 312 b cpu_rev_var_ls 313endfunc check_errata_1275112 314 315/* -------------------------------------------------- 316 * Errata Workaround for Neoverse N1 Erratum 1315703. 317 * This applies to revision <= r3p0 of Neoverse N1. 318 * Inputs: 319 * x0: variant[4:7] and revision[0:3] of current cpu. 320 * Shall clobber: x0-x17 321 * -------------------------------------------------- 322 */ 323func errata_n1_1315703_wa 324 /* Compare x0 against revision r3p1 */ 325 mov x17, x30 326 bl check_errata_1315703 327 cbz x0, 1f 328 329 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 330 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 331 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 332 3331: 334 ret x17 335endfunc errata_n1_1315703_wa 336 337func check_errata_1315703 338 /* Applies to everything <= r3p0. */ 339 mov x1, #0x30 340 b cpu_rev_var_ls 341endfunc check_errata_1315703 342 343/* -------------------------------------------------- 344 * Errata Workaround for Neoverse N1 Erratum 1542419. 345 * This applies to revisions r3p0 - r4p0 of Neoverse N1 346 * Inputs: 347 * x0: variant[4:7] and revision[0:3] of current cpu. 348 * Shall clobber: x0-x17 349 * -------------------------------------------------- 350 */ 351func errata_n1_1542419_wa 352 /* Compare x0 against revision r3p0 and r4p0 */ 353 mov x17, x30 354 bl check_errata_1542419 355 cbz x0, 1f 356 357 /* Apply instruction patching sequence */ 358 ldr x0, =0x0 359 msr CPUPSELR_EL3, x0 360 ldr x0, =0xEE670D35 361 msr CPUPOR_EL3, x0 362 ldr x0, =0xFFFF0FFF 363 msr CPUPMR_EL3, x0 364 ldr x0, =0x08000020007D 365 msr CPUPCR_EL3, x0 366 isb 3671: 368 ret x17 369endfunc errata_n1_1542419_wa 370 371func check_errata_1542419 372 /* Applies to everything r3p0 - r4p0. */ 373 mov x1, #0x30 374 mov x2, #0x40 375 b cpu_rev_var_range 376endfunc check_errata_1542419 377 378 /* -------------------------------------------------- 379 * Errata Workaround for Neoverse N1 Errata #1868343. 380 * This applies to revision <= r4p0 of Neoverse N1. 381 * This workaround is the same as the workaround for 382 * errata 1262606 and 1275112 but applies to a wider 383 * revision range. 384 * Inputs: 385 * x0: variant[4:7] and revision[0:3] of current cpu. 386 * Shall clobber: x0-x17 387 * -------------------------------------------------- 388 */ 389func errata_n1_1868343_wa 390 /* 391 * Compare x0 against revision r4p0 392 */ 393 mov x17, x30 394 bl check_errata_1868343 395 cbz x0, 1f 396 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 397 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 398 msr NEOVERSE_N1_CPUACTLR_EL1, x1 399 isb 4001: 401 ret x17 402endfunc errata_n1_1868343_wa 403 404func check_errata_1868343 405 /* Applies to everything <= r4p0 */ 406 mov x1, #0x40 407 b cpu_rev_var_ls 408endfunc check_errata_1868343 409 410 /* -------------------------------------------------- 411 * Errata Workaround for Neoverse N1 Errata #1946160. 412 * This applies to revisions r3p0, r3p1, r4p0, and 413 * r4p1 of Neoverse N1. It also exists in r0p0, r1p0, 414 * and r2p0 but there is no fix in these revisions. 415 * Inputs: 416 * x0: variant[4:7] and revision[0:3] of current cpu. 417 * Shall clobber: x0-x17 418 * -------------------------------------------------- 419 */ 420func errata_n1_1946160_wa 421 /* 422 * Compare x0 against r3p0 - r4p1 423 */ 424 mov x17, x30 425 bl check_errata_1946160 426 cbz x0, 1f 427 428 mov x0, #3 429 msr S3_6_C15_C8_0, x0 430 ldr x0, =0x10E3900002 431 msr S3_6_C15_C8_2, x0 432 ldr x0, =0x10FFF00083 433 msr S3_6_C15_C8_3, x0 434 ldr x0, =0x2001003FF 435 msr S3_6_C15_C8_1, x0 436 437 mov x0, #4 438 msr S3_6_C15_C8_0, x0 439 ldr x0, =0x10E3800082 440 msr S3_6_C15_C8_2, x0 441 ldr x0, =0x10FFF00083 442 msr S3_6_C15_C8_3, x0 443 ldr x0, =0x2001003FF 444 msr S3_6_C15_C8_1, x0 445 446 mov x0, #5 447 msr S3_6_C15_C8_0, x0 448 ldr x0, =0x10E3800200 449 msr S3_6_C15_C8_2, x0 450 ldr x0, =0x10FFF003E0 451 msr S3_6_C15_C8_3, x0 452 ldr x0, =0x2001003FF 453 msr S3_6_C15_C8_1, x0 454 455 isb 4561: 457 ret x17 458endfunc errata_n1_1946160_wa 459 460func check_errata_1946160 461 /* Applies to r3p0 - r4p1. */ 462 mov x1, #0x30 463 mov x2, #0x41 464 b cpu_rev_var_range 465endfunc check_errata_1946160 466 467func neoverse_n1_reset_func 468 mov x19, x30 469 470 bl neoverse_n1_disable_speculative_loads 471 472 /* Forces all cacheable atomic instructions to be near */ 473 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 474 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 475 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 476 isb 477 478 bl cpu_get_rev_var 479 mov x18, x0 480 481#if ERRATA_N1_1043202 482 mov x0, x18 483 bl errata_n1_1043202_wa 484#endif 485 486#if ERRATA_N1_1073348 487 mov x0, x18 488 bl errata_n1_1073348_wa 489#endif 490 491#if ERRATA_N1_1130799 492 mov x0, x18 493 bl errata_n1_1130799_wa 494#endif 495 496#if ERRATA_N1_1165347 497 mov x0, x18 498 bl errata_n1_1165347_wa 499#endif 500 501#if ERRATA_N1_1207823 502 mov x0, x18 503 bl errata_n1_1207823_wa 504#endif 505 506#if ERRATA_N1_1220197 507 mov x0, x18 508 bl errata_n1_1220197_wa 509#endif 510 511#if ERRATA_N1_1257314 512 mov x0, x18 513 bl errata_n1_1257314_wa 514#endif 515 516#if ERRATA_N1_1262606 517 mov x0, x18 518 bl errata_n1_1262606_wa 519#endif 520 521#if ERRATA_N1_1262888 522 mov x0, x18 523 bl errata_n1_1262888_wa 524#endif 525 526#if ERRATA_N1_1275112 527 mov x0, x18 528 bl errata_n1_1275112_wa 529#endif 530 531#if ERRATA_N1_1315703 532 mov x0, x18 533 bl errata_n1_1315703_wa 534#endif 535 536#if ERRATA_N1_1542419 537 mov x0, x18 538 bl errata_n1_1542419_wa 539#endif 540 541#if ERRATA_N1_1868343 542 mov x0, x18 543 bl errata_n1_1868343_wa 544#endif 545 546#if ERRATA_N1_1946160 547 mov x0, x18 548 bl errata_n1_1946160_wa 549#endif 550 551#if ENABLE_AMU 552 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 553 mrs x0, actlr_el3 554 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 555 msr actlr_el3, x0 556 557 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 558 mrs x0, actlr_el2 559 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 560 msr actlr_el2, x0 561 562 /* Enable group0 counters */ 563 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK 564 msr CPUAMCNTENSET_EL0, x0 565#endif 566 567#if NEOVERSE_Nx_EXTERNAL_LLC 568 /* Some system may have External LLC, core needs to be made aware */ 569 mrs x0, NEOVERSE_N1_CPUECTLR_EL1 570 orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT 571 msr NEOVERSE_N1_CPUECTLR_EL1, x0 572#endif 573 574#if ERRATA_DSU_936184 575 bl errata_dsu_936184_wa 576#endif 577 578 isb 579 ret x19 580endfunc neoverse_n1_reset_func 581 582 /* --------------------------------------------- 583 * HW will do the cache maintenance while powering down 584 * --------------------------------------------- 585 */ 586func neoverse_n1_core_pwr_dwn 587 /* --------------------------------------------- 588 * Enable CPU power down bit in power control register 589 * --------------------------------------------- 590 */ 591 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 592 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 593 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 594 isb 595 ret 596endfunc neoverse_n1_core_pwr_dwn 597 598#if REPORT_ERRATA 599/* 600 * Errata printing function for Neoverse N1. Must follow AAPCS. 601 */ 602func neoverse_n1_errata_report 603 stp x8, x30, [sp, #-16]! 604 605 bl cpu_get_rev_var 606 mov x8, x0 607 608 /* 609 * Report all errata. The revision-variant information is passed to 610 * checking functions of each errata. 611 */ 612 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 613 report_errata ERRATA_N1_1073348, neoverse_n1, 1073348 614 report_errata ERRATA_N1_1130799, neoverse_n1, 1130799 615 report_errata ERRATA_N1_1165347, neoverse_n1, 1165347 616 report_errata ERRATA_N1_1207823, neoverse_n1, 1207823 617 report_errata ERRATA_N1_1220197, neoverse_n1, 1220197 618 report_errata ERRATA_N1_1257314, neoverse_n1, 1257314 619 report_errata ERRATA_N1_1262606, neoverse_n1, 1262606 620 report_errata ERRATA_N1_1262888, neoverse_n1, 1262888 621 report_errata ERRATA_N1_1275112, neoverse_n1, 1275112 622 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 623 report_errata ERRATA_N1_1542419, neoverse_n1, 1542419 624 report_errata ERRATA_N1_1868343, neoverse_n1, 1868343 625 report_errata ERRATA_N1_1946160, neoverse_n1, 1946160 626 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 627 628 ldp x8, x30, [sp], #16 629 ret 630endfunc neoverse_n1_errata_report 631#endif 632 633/* 634 * Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB 635 * inner-shareable invalidation to an arbitrary address followed by a DSB. 636 * 637 * x1: Exception Syndrome 638 */ 639func neoverse_n1_errata_ic_trap_handler 640 cmp x1, #NEOVERSE_N1_EC_IC_TRAP 641 b.ne 1f 642 tlbi vae3is, xzr 643 dsb sy 644 645 # Skip the IC instruction itself 646 mrs x3, elr_el3 647 add x3, x3, #4 648 msr elr_el3, x3 649 650 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 651 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 652 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 653 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 654 655#if IMAGE_BL31 && RAS_EXTENSION 656 /* 657 * Issue Error Synchronization Barrier to synchronize SErrors before 658 * exiting EL3. We're running with EAs unmasked, so any synchronized 659 * errors would be taken immediately; therefore no need to inspect 660 * DISR_EL1 register. 661 */ 662 esb 663#endif 664 exception_return 6651: 666 ret 667endfunc neoverse_n1_errata_ic_trap_handler 668 669 /* --------------------------------------------- 670 * This function provides neoverse_n1 specific 671 * register information for crash reporting. 672 * It needs to return with x6 pointing to 673 * a list of register names in ascii and 674 * x8 - x15 having values of registers to be 675 * reported. 676 * --------------------------------------------- 677 */ 678.section .rodata.neoverse_n1_regs, "aS" 679neoverse_n1_regs: /* The ascii list of register names to be reported */ 680 .asciz "cpuectlr_el1", "" 681 682func neoverse_n1_cpu_reg_dump 683 adr x6, neoverse_n1_regs 684 mrs x8, NEOVERSE_N1_CPUECTLR_EL1 685 ret 686endfunc neoverse_n1_cpu_reg_dump 687 688declare_cpu_ops_eh neoverse_n1, NEOVERSE_N1_MIDR, \ 689 neoverse_n1_reset_func, \ 690 neoverse_n1_errata_ic_trap_handler, \ 691 neoverse_n1_core_pwr_dwn 692