1/* 2 * Copyright (c) 2019-2020, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* --------------------------------------------- 25 * HW will do the cache maintenance while powering down 26 * --------------------------------------------- 27 */ 28func neoverse_v1_core_pwr_dwn 29 /* --------------------------------------------- 30 * Enable CPU power down bit in power control register 31 * --------------------------------------------- 32 */ 33 mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1 34 orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 35 msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0 36 isb 37 ret 38endfunc neoverse_v1_core_pwr_dwn 39 40 /* 41 * Errata printing function for Neoverse V1. Must follow AAPCS. 42 */ 43#if REPORT_ERRATA 44func neoverse_v1_errata_report 45 ret 46endfunc neoverse_v1_errata_report 47#endif 48 49func neoverse_v1_reset_func 50 mov x19, x30 51 52 /* Disable speculative loads */ 53 msr SSBS, xzr 54 55 isb 56 ret x19 57endfunc neoverse_v1_reset_func 58 59 /* --------------------------------------------- 60 * This function provides Neoverse-V1 specific 61 * register information for crash reporting. 62 * It needs to return with x6 pointing to 63 * a list of register names in ascii and 64 * x8 - x15 having values of registers to be 65 * reported. 66 * --------------------------------------------- 67 */ 68.section .rodata.neoverse_v1_regs, "aS" 69neoverse_v1_regs: /* The ascii list of register names to be reported */ 70 .asciz "cpuectlr_el1", "" 71 72func neoverse_v1_cpu_reg_dump 73 adr x6, neoverse_v1_regs 74 mrs x8, NEOVERSE_V1_CPUECTLR_EL1 75 ret 76endfunc neoverse_v1_cpu_reg_dump 77 78declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \ 79 neoverse_v1_reset_func, \ 80 neoverse_v1_core_pwr_dwn 81