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1//===-- llvm/Target/TargetOpcodes.def - Target Indep Opcodes ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the target independent instruction opcodes.
11//
12//===----------------------------------------------------------------------===//
13
14// NOTE: NO INCLUDE GUARD DESIRED!
15
16/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value.
17///
18#ifndef HANDLE_TARGET_OPCODE
19#define HANDLE_TARGET_OPCODE(OPC, NUM)
20#endif
21
22/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode.
23///
24#ifndef HANDLE_TARGET_OPCODE_MARKER
25#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC)
26#endif
27
28/// Every instruction defined here must also appear in Target.td.
29///
30HANDLE_TARGET_OPCODE(PHI, 0)
31HANDLE_TARGET_OPCODE(INLINEASM, 1)
32HANDLE_TARGET_OPCODE(CFI_INSTRUCTION, 2)
33HANDLE_TARGET_OPCODE(EH_LABEL, 3)
34HANDLE_TARGET_OPCODE(GC_LABEL, 4)
35
36/// KILL - This instruction is a noop that is used only to adjust the
37/// liveness of registers. This can be useful when dealing with
38/// sub-registers.
39HANDLE_TARGET_OPCODE(KILL, 5)
40
41/// EXTRACT_SUBREG - This instruction takes two operands: a register
42/// that has subregisters, and a subregister index. It returns the
43/// extracted subregister value. This is commonly used to implement
44/// truncation operations on target architectures which support it.
45HANDLE_TARGET_OPCODE(EXTRACT_SUBREG, 6)
46
47/// INSERT_SUBREG - This instruction takes three operands: a register that
48/// has subregisters, a register providing an insert value, and a
49/// subregister index. It returns the value of the first register with the
50/// value of the second register inserted. The first register is often
51/// defined by an IMPLICIT_DEF, because it is commonly used to implement
52/// anyext operations on target architectures which support it.
53HANDLE_TARGET_OPCODE(INSERT_SUBREG, 7)
54
55/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
56HANDLE_TARGET_OPCODE(IMPLICIT_DEF, 8)
57
58/// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
59/// the first operand is an immediate integer constant. This constant is
60/// often zero, because it is commonly used to assert that the instruction
61/// defining the register implicitly clears the high bits.
62HANDLE_TARGET_OPCODE(SUBREG_TO_REG, 9)
63
64/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
65/// register-to-register copy into a specific register class. This is only
66/// used between instruction selection and MachineInstr creation, before
67/// virtual registers have been created for all the instructions, and it's
68/// only needed in cases where the register classes implied by the
69/// instructions are insufficient. It is emitted as a COPY MachineInstr.
70HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS, 10)
71
72/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
73HANDLE_TARGET_OPCODE(DBG_VALUE, 11)
74
75/// REG_SEQUENCE - This variadic instruction is used to form a register that
76/// represents a consecutive sequence of sub-registers. It's used as a
77/// register coalescing / allocation aid and must be eliminated before code
78/// emission.
79// In SDNode form, the first operand encodes the register class created by
80// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
81// pair.  Once it has been lowered to a MachineInstr, the regclass operand
82// is no longer present.
83/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
84/// After register coalescing references of v1024 should be replace with
85/// v1027:3, v1025 with v1027:4, etc.
86HANDLE_TARGET_OPCODE(REG_SEQUENCE, 12)
87
88/// COPY - Target-independent register copy. This instruction can also be
89/// used to copy between subregisters of virtual registers.
90HANDLE_TARGET_OPCODE(COPY, 13)
91
92/// BUNDLE - This instruction represents an instruction bundle. Instructions
93/// which immediately follow a BUNDLE instruction which are marked with
94/// 'InsideBundle' flag are inside the bundle.
95HANDLE_TARGET_OPCODE(BUNDLE, 14)
96
97/// Lifetime markers.
98HANDLE_TARGET_OPCODE(LIFETIME_START, 15)
99HANDLE_TARGET_OPCODE(LIFETIME_END, 16)
100
101/// A Stackmap instruction captures the location of live variables at its
102/// position in the instruction stream. It is followed by a shadow of bytes
103/// that must lie within the function and not contain another stackmap.
104HANDLE_TARGET_OPCODE(STACKMAP, 17)
105
106/// Patchable call instruction - this instruction represents a call to a
107/// constant address, followed by a series of NOPs. It is intended to
108/// support optimizations for dynamic languages (such as javascript) that
109/// rewrite calls to runtimes with more efficient code sequences.
110/// This also implies a stack map.
111HANDLE_TARGET_OPCODE(PATCHPOINT, 18)
112
113/// This pseudo-instruction loads the stack guard value. Targets which need
114/// to prevent the stack guard value or address from being spilled to the
115/// stack should override TargetLowering::emitLoadStackGuardNode and
116/// additionally expand this pseudo after register allocation.
117HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD, 19)
118
119/// Call instruction with associated vm state for deoptimization and list
120/// of live pointers for relocation by the garbage collector.  It is
121/// intended to support garbage collection with fully precise relocating
122/// collectors and deoptimizations in either the callee or caller.
123HANDLE_TARGET_OPCODE(STATEPOINT, 20)
124
125/// Instruction that records the offset of a local stack allocation passed to
126/// llvm.localescape. It has two arguments: the symbol for the label and the
127/// frame index of the local stack allocation.
128HANDLE_TARGET_OPCODE(LOCAL_ESCAPE, 21)
129
130/// Loading instruction that may page fault, bundled with associated
131/// information on how to handle such a page fault.  It is intended to support
132/// "zero cost" null checks in managed languages by allowing LLVM to fold
133/// comparisons into existing memory operations.
134HANDLE_TARGET_OPCODE(FAULTING_LOAD_OP, 22)
135
136/// Wraps a machine instruction to add patchability constraints.  An
137/// instruction wrapped in PATCHABLE_OP has to either have a minimum
138/// size or be preceded with a nop of that size.  The first operand is
139/// an immediate denoting the minimum size of the instruction, the
140/// second operand is an immediate denoting the opcode of the original
141/// instruction.  The rest of the operands are the operands of the
142/// original instruction.
143HANDLE_TARGET_OPCODE(PATCHABLE_OP, 23)
144
145/// This is a marker instruction which gets translated into a nop sled, useful
146/// for inserting instrumentation instructions at runtime.
147HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER, 24)
148
149/// Wraps a return instruction and its operands to enable adding nop sleds
150/// either before or after the return. The nop sleds are useful for inserting
151/// instrumentation instructions at runtime.
152HANDLE_TARGET_OPCODE(PATCHABLE_RET, 25)
153
154/// The following generic opcodes are not supposed to appear after ISel.
155/// This is something we might want to relax, but for now, this is convenient
156/// to produce diagnostics.
157
158/// Generic ADD instruction. This is an integer add.
159HANDLE_TARGET_OPCODE(G_ADD, 26)
160HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD)
161
162/// Generic Bitwise-OR instruction.
163HANDLE_TARGET_OPCODE(G_OR, 27)
164
165/// Generic BRANCH instruction. This is an unconditional branch.
166HANDLE_TARGET_OPCODE(G_BR, 28)
167
168// TODO: Add more generic opcodes as we move along.
169
170/// Marker for the end of the generic opcode.
171/// This is used to check if an opcode is in the range of the
172/// generic opcodes.
173HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_BR)
174
175/// BUILTIN_OP_END - This must be the last enum value in this list.
176/// The target-specific post-isel opcode values start here.
177HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END)
178