1 //==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the subtarget options of a Target machine. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H 15 #define LLVM_TARGET_TARGETSUBTARGETINFO_H 16 17 #include "llvm/CodeGen/PBQPRAConstraint.h" 18 #include "llvm/CodeGen/SchedulerRegistry.h" 19 #include "llvm/CodeGen/ScheduleDAGMutation.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/Support/CodeGen.h" 22 #include <vector> 23 24 namespace llvm { 25 26 class CallLowering; 27 class DataLayout; 28 class MachineFunction; 29 class MachineInstr; 30 class RegisterBankInfo; 31 class SDep; 32 class SUnit; 33 class TargetFrameLowering; 34 class TargetInstrInfo; 35 class TargetLowering; 36 class TargetRegisterClass; 37 class TargetRegisterInfo; 38 class TargetSchedModel; 39 class SelectionDAGTargetInfo; 40 struct MachineSchedPolicy; 41 template <typename T> class SmallVectorImpl; 42 43 //===----------------------------------------------------------------------===// 44 /// 45 /// TargetSubtargetInfo - Generic base class for all target subtargets. All 46 /// Target-specific options that control code generation and printing should 47 /// be exposed through a TargetSubtargetInfo-derived class. 48 /// 49 class TargetSubtargetInfo : public MCSubtargetInfo { 50 TargetSubtargetInfo(const TargetSubtargetInfo &) = delete; 51 void operator=(const TargetSubtargetInfo &) = delete; 52 TargetSubtargetInfo() = delete; 53 54 protected: // Can only create subclasses... 55 TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS, 56 ArrayRef<SubtargetFeatureKV> PF, 57 ArrayRef<SubtargetFeatureKV> PD, 58 const SubtargetInfoKV *ProcSched, 59 const MCWriteProcResEntry *WPR, 60 const MCWriteLatencyEntry *WL, 61 const MCReadAdvanceEntry *RA, const InstrStage *IS, 62 const unsigned *OC, const unsigned *FP); 63 64 public: 65 // AntiDepBreakMode - Type of anti-dependence breaking that should 66 // be performed before post-RA scheduling. 67 typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode; 68 typedef SmallVectorImpl<const TargetRegisterClass *> RegClassVector; 69 70 virtual ~TargetSubtargetInfo(); 71 72 // Interfaces to the major aspects of target machine information: 73 // 74 // -- Instruction opcode and operand information 75 // -- Pipelines and scheduling information 76 // -- Stack frame information 77 // -- Selection DAG lowering information 78 // -- Call lowering information 79 // 80 // N.B. These objects may change during compilation. It's not safe to cache 81 // them between functions. getInstrInfo()82 virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; } getFrameLowering()83 virtual const TargetFrameLowering *getFrameLowering() const { 84 return nullptr; 85 } getTargetLowering()86 virtual const TargetLowering *getTargetLowering() const { return nullptr; } getSelectionDAGInfo()87 virtual const SelectionDAGTargetInfo *getSelectionDAGInfo() const { 88 return nullptr; 89 } getCallLowering()90 virtual const CallLowering *getCallLowering() const { return nullptr; } 91 /// Target can subclass this hook to select a different DAG scheduler. 92 virtual RegisterScheduler::FunctionPassCtor getDAGScheduler(CodeGenOpt::Level)93 getDAGScheduler(CodeGenOpt::Level) const { 94 return nullptr; 95 } 96 97 /// getRegisterInfo - If register information is available, return it. If 98 /// not, return null. 99 /// getRegisterInfo()100 virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; } 101 102 /// If the information for the register banks is available, return it. 103 /// Otherwise return nullptr. getRegBankInfo()104 virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr; } 105 106 /// getInstrItineraryData - Returns instruction itinerary data for the target 107 /// or specific subtarget. 108 /// getInstrItineraryData()109 virtual const InstrItineraryData *getInstrItineraryData() const { 110 return nullptr; 111 } 112 113 /// Resolve a SchedClass at runtime, where SchedClass identifies an 114 /// MCSchedClassDesc with the isVariant property. This may return the ID of 115 /// another variant SchedClass, but repeated invocation must quickly terminate 116 /// in a nonvariant SchedClass. resolveSchedClass(unsigned SchedClass,const MachineInstr * MI,const TargetSchedModel * SchedModel)117 virtual unsigned resolveSchedClass(unsigned SchedClass, 118 const MachineInstr *MI, 119 const TargetSchedModel *SchedModel) const { 120 return 0; 121 } 122 123 /// \brief True if the subtarget should run MachineScheduler after aggressive 124 /// coalescing. 125 /// 126 /// This currently replaces the SelectionDAG scheduler with the "source" order 127 /// scheduler (though see below for an option to turn this off and use the 128 /// TargetLowering preference). It does not yet disable the postRA scheduler. 129 virtual bool enableMachineScheduler() const; 130 131 /// \brief True if the machine scheduler should disable the TLI preference 132 /// for preRA scheduling with the source level scheduler. enableMachineSchedDefaultSched()133 virtual bool enableMachineSchedDefaultSched() const { return true; } 134 135 /// \brief True if the subtarget should enable joining global copies. 136 /// 137 /// By default this is enabled if the machine scheduler is enabled, but 138 /// can be overridden. 139 virtual bool enableJoinGlobalCopies() const; 140 141 /// True if the subtarget should run a scheduler after register allocation. 142 /// 143 /// By default this queries the PostRAScheduling bit in the scheduling model 144 /// which is the preferred way to influence this. 145 virtual bool enablePostRAScheduler() const; 146 147 /// \brief True if the subtarget should run the atomic expansion pass. 148 virtual bool enableAtomicExpand() const; 149 150 /// \brief Override generic scheduling policy within a region. 151 /// 152 /// This is a convenient way for targets that don't provide any custom 153 /// scheduling heuristics (no custom MachineSchedStrategy) to make 154 /// changes to the generic scheduling policy. overrideSchedPolicy(MachineSchedPolicy & Policy,unsigned NumRegionInstrs)155 virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, 156 unsigned NumRegionInstrs) const {} 157 158 // \brief Perform target specific adjustments to the latency of a schedule 159 // dependency. adjustSchedDependency(SUnit * def,SUnit * use,SDep & dep)160 virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {} 161 162 // For use with PostRAScheduling: get the anti-dependence breaking that should 163 // be performed before post-RA scheduling. getAntiDepBreakMode()164 virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; } 165 166 // For use with PostRAScheduling: in CriticalPathRCs, return any register 167 // classes that should only be considered for anti-dependence breaking if they 168 // are on the critical path. getCriticalPathRCs(RegClassVector & CriticalPathRCs)169 virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 170 return CriticalPathRCs.clear(); 171 } 172 173 // \brief Provide an ordered list of schedule DAG mutations for the post-RA 174 // scheduler. getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>> & Mutations)175 virtual void getPostRAMutations( 176 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const { 177 } 178 179 // For use with PostRAScheduling: get the minimum optimization level needed 180 // to enable post-RA scheduling. getOptLevelToEnablePostRAScheduler()181 virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const { 182 return CodeGenOpt::Default; 183 } 184 185 /// \brief True if the subtarget should run the local reassignment 186 /// heuristic of the register allocator. 187 /// This heuristic may be compile time intensive, \p OptLevel provides 188 /// a finer grain to tune the register allocator. 189 virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const; 190 191 /// \brief Enable use of alias analysis during code generation (during MI 192 /// scheduling, DAGCombine, etc.). 193 virtual bool useAA() const; 194 195 /// \brief Enable the use of the early if conversion pass. enableEarlyIfConversion()196 virtual bool enableEarlyIfConversion() const { return false; } 197 198 /// \brief Return PBQPConstraint(s) for the target. 199 /// 200 /// Override to provide custom PBQP constraints. getCustomPBQPConstraints()201 virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const { 202 return nullptr; 203 } 204 205 /// Enable tracking of subregister liveness in register allocator. enableSubRegLiveness()206 virtual bool enableSubRegLiveness() const { return false; } 207 }; 208 209 } // End llvm namespace 210 211 #endif 212