1; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 2 3declare i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a) 4 5; GCN-LABEL: {{^}}frexp_exp_f16 6; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] 7; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]] 8; GCN: buffer_store_short v[[R_I16]] 9define amdgpu_kernel void @frexp_exp_f16( 10 i16 addrspace(1)* %r, 11 half addrspace(1)* %a) { 12entry: 13 %a.val = load half, half addrspace(1)* %a 14 %r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val) 15 store i16 %r.val, i16 addrspace(1)* %r 16 ret void 17} 18 19; GCN-LABEL: {{^}}frexp_exp_f16_sext 20; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] 21; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]] 22; VI: v_bfe_i32 v[[R_I32:[0-9]+]], v[[R_I16]], 0, 16{{$}} 23; GCN: buffer_store_dword v[[R_I32]] 24define amdgpu_kernel void @frexp_exp_f16_sext( 25 i32 addrspace(1)* %r, 26 half addrspace(1)* %a) { 27entry: 28 %a.val = load half, half addrspace(1)* %a 29 %r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val) 30 %r.val.sext = sext i16 %r.val to i32 31 store i32 %r.val.sext, i32 addrspace(1)* %r 32 ret void 33} 34 35; GCN-LABEL: {{^}}frexp_exp_f16_zext 36; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] 37; VI: v_frexp_exp_i16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]] 38; VI: v_and_b32_e32 v[[R_I32:[0-9]+]], 0xffff, v[[R_I16]] 39; GCN: buffer_store_dword v[[R_I32]] 40define amdgpu_kernel void @frexp_exp_f16_zext( 41 i32 addrspace(1)* %r, 42 half addrspace(1)* %a) { 43entry: 44 %a.val = load half, half addrspace(1)* %a 45 %r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val) 46 %r.val.zext = zext i16 %r.val to i32 47 store i32 %r.val.zext, i32 addrspace(1)* %r 48 ret void 49} 50