1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef LS_DEF_H 8 #define LS_DEF_H 9 10 #include <platform_def.h> 11 12 #include <arch.h> 13 #include <common/tbbr/tbbr_img_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <lib/utils_def.h> 16 #include <plat/common/common_def.h> 17 18 /****************************************************************************** 19 * Definitions common to all ARM standard platforms 20 *****************************************************************************/ 21 /* Special value used to verify platform parameters from BL2 to BL31 */ 22 #define LS_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 23 24 #define LS_CACHE_WRITEBACK_SHIFT 6 25 26 /* 27 * Macros mapping the MPIDR Affinity levels to Layerscape Platform Power levels. The 28 * power levels have a 1:1 mapping with the MPIDR affinity levels. 29 */ 30 #define LS_PWR_LVL0 MPIDR_AFFLVL0 31 #define LS_PWR_LVL1 MPIDR_AFFLVL1 32 #define LS_PWR_LVL2 MPIDR_AFFLVL2 33 34 /* 35 * Macros for local power states in Layerscape platforms encoded by State-ID field 36 * within the power-state parameter. 37 */ 38 /* Local power state for power domains in Run state. */ 39 #define LS_LOCAL_STATE_RUN U(0) 40 /* Local power state for retention. Valid only for CPU power domains */ 41 #define LS_LOCAL_STATE_RET U(1) 42 /* 43 * Local power state for OFF/power-down. Valid for CPU and cluster power 44 * domains 45 */ 46 #define LS_LOCAL_STATE_OFF U(2) 47 48 #define LS_MAP_NS_DRAM MAP_REGION_FLAT( \ 49 (LS_NS_DRAM_BASE), \ 50 LS_DRAM1_SIZE, \ 51 MT_DEVICE | MT_RW | MT_NS) 52 53 #define LS_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 54 TSP_SEC_MEM_BASE, \ 55 TSP_SEC_MEM_SIZE, \ 56 MT_DEVICE | MT_RW | MT_SECURE) 57 58 59 #define LS_MAP_FLASH0_RW MAP_REGION_FLAT(PLAT_LS_FLASH_BASE,\ 60 PLAT_LS_FLASH_SIZE, \ 61 MT_DEVICE | MT_RW) 62 63 #define LS_MAP_CCSR MAP_REGION_FLAT(PLAT_LS_CCSR_BASE, \ 64 PLAT_LS_CCSR_SIZE, \ 65 MT_DEVICE | MT_RW | MT_SECURE) 66 67 68 #define LS_MAP_CONSOLE MAP_REGION_FLAT(PLAT_LS1043_DUART1_BASE, \ 69 PLAT_LS1043_DUART_SIZE, \ 70 MT_DEVICE | MT_RW | MT_NS) 71 72 /* 73 * The number of regions like RO(code), coherent and data required by 74 * different BL stages which need to be mapped in the MMU. 75 */ 76 /****************************************************************************** 77 * Required platform porting definitions common to all ARM standard platforms 78 *****************************************************************************/ 79 80 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 81 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 82 83 /* 84 * This macro defines the deepest retention state possible. A higher state 85 * id will represent an invalid or a power down state. 86 */ 87 #define PLAT_MAX_RET_STATE LS_LOCAL_STATE_RET 88 89 /* 90 * This macro defines the deepest power down states possible. Any state ID 91 * higher than this is invalid. 92 */ 93 #define PLAT_MAX_OFF_STATE LS_LOCAL_STATE_OFF 94 95 /* 96 * Some data must be aligned on the biggest cache line size in the platform. 97 * This is known only to the platform as it might have a combination of 98 * integrated and external caches. 99 */ 100 #define CACHE_WRITEBACK_GRANULE (1 << LS_CACHE_WRITEBACK_SHIFT) 101 102 /* 103 * One cache line needed for bakery locks on Layerscape platforms 104 */ 105 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 106 107 #endif /* LS_DEF_H */ 108