1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #ifndef MSS_MEM_H 9 #define MSS_MEM_H 10 11 /* MSS SRAM Memory base */ 12 #define MSS_SRAM_PM_CONTROL_BASE (MVEBU_REGS_BASE + 0x520000) 13 14 enum mss_pm_ctrl_handshake { 15 MSS_UN_INITIALIZED = 0, 16 MSS_COMPATIBILITY_ERROR = 1, 17 MSS_ACKNOWLEDGMENT = 2, 18 HOST_ACKNOWLEDGMENT = 3 19 }; 20 21 enum mss_pm_ctrl_rtos_env { 22 MSS_MULTI_PROCESS_ENV = 0, 23 MSS_SINGLE_PROCESS_ENV = 1, 24 MSS_MAX_PROCESS_ENV 25 }; 26 27 struct mss_pm_ctrl_block { 28 /* This field is used to synchronize the Host 29 * and MSS initialization sequence 30 * Valid Values 31 * 0 - Un-Initialized 32 * 1 - Compatibility Error 33 * 2 - MSS Acknowledgment 34 * 3 - Host Acknowledgment 35 */ 36 unsigned int handshake; 37 38 /* 39 * This field include Host IPC version. Once received by the MSS 40 * It will be compared to MSS IPC version and set MSS Acknowledge to 41 * "compatibility error" in case there is no match 42 */ 43 unsigned int ipc_version; 44 unsigned int ipc_base_address; 45 unsigned int ipc_state; 46 47 /* Following fields defines firmware core architecture */ 48 unsigned int num_of_cores; 49 unsigned int num_of_clusters; 50 unsigned int num_of_cores_per_cluster; 51 52 /* Following fields define pm trace debug base address */ 53 unsigned int pm_trace_ctrl_base_address; 54 unsigned int pm_trace_info_base_address; 55 unsigned int pm_trace_info_core_size; 56 57 unsigned int ctrl_blk_size; 58 }; 59 60 #endif /* MSS_MEM_H */ 61