1 /*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <string.h>
10
11 #include <arch_helpers.h>
12 #include <bl1/tbbr/tbbr_img_desc.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <drivers/arm/pl011.h>
16 #include <drivers/mmc.h>
17 #include <drivers/synopsys/dw_mmc.h>
18 #include <lib/mmio.h>
19 #include <plat/common/platform.h>
20
21 #include <hi6220.h>
22 #include <hikey_def.h>
23 #include <hikey_layout.h>
24
25 #include "hikey_private.h"
26
27 /* Data structure which holds the extents of the trusted RAM for BL1 */
28 static meminfo_t bl1_tzram_layout;
29 static console_t console;
30
31 enum {
32 BOOT_NORMAL = 0,
33 BOOT_USB_DOWNLOAD,
34 BOOT_UART_DOWNLOAD,
35 };
36
bl1_plat_sec_mem_layout(void)37 meminfo_t *bl1_plat_sec_mem_layout(void)
38 {
39 return &bl1_tzram_layout;
40 }
41
42 /*
43 * Perform any BL1 specific platform actions.
44 */
bl1_early_platform_setup(void)45 void bl1_early_platform_setup(void)
46 {
47 /* Initialize the console to provide early debug support */
48 console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ,
49 PL011_BAUDRATE, &console);
50
51 /* Allow BL1 to see the whole Trusted RAM */
52 bl1_tzram_layout.total_base = BL1_RW_BASE;
53 bl1_tzram_layout.total_size = BL1_RW_SIZE;
54
55 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
56 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
57 }
58
59 /*
60 * Perform the very early platform specific architecture setup here. At the
61 * moment this only does basic initialization. Later architectural setup
62 * (bl1_arch_setup()) does not do anything platform specific.
63 */
bl1_plat_arch_setup(void)64 void bl1_plat_arch_setup(void)
65 {
66 hikey_init_mmu_el3(bl1_tzram_layout.total_base,
67 bl1_tzram_layout.total_size,
68 BL1_RO_BASE,
69 BL1_RO_LIMIT,
70 BL_COHERENT_RAM_BASE,
71 BL_COHERENT_RAM_END);
72 }
73
74 /*
75 * Function which will perform any remaining platform-specific setup that can
76 * occur after the MMU and data cache have been enabled.
77 */
bl1_platform_setup(void)78 void bl1_platform_setup(void)
79 {
80 dw_mmc_params_t params;
81 struct mmc_device_info info;
82
83 assert((HIKEY_BL1_MMC_DESC_BASE >= SRAM_BASE) &&
84 ((SRAM_BASE + SRAM_SIZE) >=
85 (HIKEY_BL1_MMC_DATA_BASE + HIKEY_BL1_MMC_DATA_SIZE)));
86 hikey_sp804_init();
87 hikey_gpio_init();
88 hikey_pmussi_init();
89 hikey_hi6553_init();
90
91 hikey_rtc_init();
92
93 hikey_mmc_pll_init();
94
95 memset(¶ms, 0, sizeof(dw_mmc_params_t));
96 params.reg_base = DWMMC0_BASE;
97 params.desc_base = HIKEY_BL1_MMC_DESC_BASE;
98 params.desc_size = 1 << 20;
99 params.clk_rate = 24 * 1000 * 1000;
100 params.bus_width = MMC_BUS_WIDTH_8;
101 params.flags = MMC_FLAG_CMD23;
102 info.mmc_dev_type = MMC_IS_EMMC;
103 dw_mmc_init(¶ms, &info);
104
105 hikey_io_setup();
106 }
107
108 /*
109 * The following function checks if Firmware update is needed,
110 * by checking if TOC in FIP image is valid or not.
111 */
bl1_plat_get_next_image_id(void)112 unsigned int bl1_plat_get_next_image_id(void)
113 {
114 int32_t boot_mode;
115 unsigned int ret;
116
117 boot_mode = mmio_read_32(ONCHIPROM_PARAM_BASE);
118 switch (boot_mode) {
119 case BOOT_USB_DOWNLOAD:
120 case BOOT_UART_DOWNLOAD:
121 ret = NS_BL1U_IMAGE_ID;
122 break;
123 default:
124 WARN("Invalid boot mode is found:%d\n", boot_mode);
125 panic();
126 }
127 return ret;
128 }
129
bl1_plat_get_image_desc(unsigned int image_id)130 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id)
131 {
132 unsigned int index = 0;
133
134 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) {
135 if (bl1_tbbr_image_descs[index].image_id == image_id)
136 return &bl1_tbbr_image_descs[index];
137
138 index++;
139 }
140
141 return NULL;
142 }
143
bl1_plat_set_ep_info(unsigned int image_id,entry_point_info_t * ep_info)144 void bl1_plat_set_ep_info(unsigned int image_id,
145 entry_point_info_t *ep_info)
146 {
147 uint64_t data = 0;
148
149 if (image_id == BL2_IMAGE_ID)
150 panic();
151 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE);
152 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data));
153 do {
154 data |= 3 << 20;
155 __asm__ volatile ("msr cpacr_el1, %0" : : "r"(data));
156 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data));
157 } while ((data & (3 << 20)) != (3 << 20));
158 INFO("cpacr_el1:0x%llx\n", data);
159
160 ep_info->args.arg0 = 0xffff & read_mpidr();
161 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
162 DISABLE_ALL_EXCEPTIONS);
163 }
164