1 /*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <string.h>
10
11 #include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/
12
13 #include <arch_helpers.h>
14 #include <common/bl_common.h>
15 #include <common/debug.h>
16 #include <common/desc_image_load.h>
17 #include <drivers/arm/pl011.h>
18 #include <drivers/delay_timer.h>
19 #include <drivers/mmc.h>
20 #include <drivers/synopsys/dw_mmc.h>
21 #include <lib/mmio.h>
22 #ifdef SPD_opteed
23 #include <lib/optee_utils.h>
24 #endif
25 #include <plat/common/platform.h>
26
27 #include <hi6220.h>
28 #include <hisi_mcu.h>
29 #include <hisi_sram_map.h>
30 #include "hikey_private.h"
31
32 #define BL2_RW_BASE (BL_CODE_END)
33
34 static meminfo_t bl2_el3_tzram_layout;
35 static console_t console;
36
37 enum {
38 BOOT_MODE_RECOVERY = 0,
39 BOOT_MODE_NORMAL,
40 BOOT_MODE_MASK = 1,
41 };
42
43 /*******************************************************************************
44 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
45 * Return 0 on success, -1 otherwise.
46 ******************************************************************************/
plat_hikey_bl2_handle_scp_bl2(image_info_t * scp_bl2_image_info)47 int plat_hikey_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
48 {
49 /* Enable MCU SRAM */
50 hisi_mcu_enable_sram();
51
52 /* Load MCU binary into SRAM */
53 hisi_mcu_load_image(scp_bl2_image_info->image_base,
54 scp_bl2_image_info->image_size);
55 /* Let MCU running */
56 hisi_mcu_start_run();
57
58 INFO("%s: MCU PC is at 0x%x\n",
59 __func__, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2));
60 INFO("%s: AO_SC_PERIPH_CLKSTAT4 is 0x%x\n",
61 __func__, mmio_read_32(AO_SC_PERIPH_CLKSTAT4));
62 return 0;
63 }
64
65 /*******************************************************************************
66 * Gets SPSR for BL32 entry
67 ******************************************************************************/
hikey_get_spsr_for_bl32_entry(void)68 uint32_t hikey_get_spsr_for_bl32_entry(void)
69 {
70 /*
71 * The Secure Payload Dispatcher service is responsible for
72 * setting the SPSR prior to entry into the BL3-2 image.
73 */
74 return 0;
75 }
76
77 /*******************************************************************************
78 * Gets SPSR for BL33 entry
79 ******************************************************************************/
80 #ifdef __aarch64__
hikey_get_spsr_for_bl33_entry(void)81 uint32_t hikey_get_spsr_for_bl33_entry(void)
82 {
83 unsigned int mode;
84 uint32_t spsr;
85
86 /* Figure out what mode we enter the non-secure world in */
87 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
88
89 /*
90 * TODO: Consider the possibility of specifying the SPSR in
91 * the FIP ToC and allowing the platform to have a say as
92 * well.
93 */
94 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
95 return spsr;
96 }
97 #else
hikey_get_spsr_for_bl33_entry(void)98 uint32_t hikey_get_spsr_for_bl33_entry(void)
99 {
100 unsigned int hyp_status, mode, spsr;
101
102 hyp_status = GET_VIRT_EXT(read_id_pfr1());
103
104 mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
105
106 /*
107 * TODO: Consider the possibility of specifying the SPSR in
108 * the FIP ToC and allowing the platform to have a say as
109 * well.
110 */
111 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
112 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
113 return spsr;
114 }
115 #endif /* __aarch64__ */
116
bl2_plat_handle_pre_image_load(unsigned int image_id)117 int bl2_plat_handle_pre_image_load(unsigned int image_id)
118 {
119 return hikey_set_fip_addr(image_id, "fastboot");
120 }
121
hikey_bl2_handle_post_image_load(unsigned int image_id)122 int hikey_bl2_handle_post_image_load(unsigned int image_id)
123 {
124 int err = 0;
125 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
126 #ifdef SPD_opteed
127 bl_mem_params_node_t *pager_mem_params = NULL;
128 bl_mem_params_node_t *paged_mem_params = NULL;
129 #endif
130 assert(bl_mem_params);
131
132 switch (image_id) {
133 #ifdef __aarch64__
134 case BL32_IMAGE_ID:
135 #ifdef SPD_opteed
136 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
137 assert(pager_mem_params);
138
139 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
140 assert(paged_mem_params);
141
142 err = parse_optee_header(&bl_mem_params->ep_info,
143 &pager_mem_params->image_info,
144 &paged_mem_params->image_info);
145 if (err != 0) {
146 WARN("OPTEE header parse error.\n");
147 }
148 #endif
149 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl32_entry();
150 break;
151 #endif
152
153 case BL33_IMAGE_ID:
154 /* BL33 expects to receive the primary CPU MPID (through r0) */
155 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
156 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl33_entry();
157 break;
158
159 #ifdef SCP_BL2_BASE
160 case SCP_BL2_IMAGE_ID:
161 /* The subsequent handling of SCP_BL2 is platform specific */
162 err = plat_hikey_bl2_handle_scp_bl2(&bl_mem_params->image_info);
163 if (err) {
164 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
165 }
166 break;
167 #endif
168 default:
169 /* Do nothing in default case */
170 break;
171 }
172
173 return err;
174 }
175
176 /*******************************************************************************
177 * This function can be used by the platforms to update/use image
178 * information for given `image_id`.
179 ******************************************************************************/
bl2_plat_handle_post_image_load(unsigned int image_id)180 int bl2_plat_handle_post_image_load(unsigned int image_id)
181 {
182 return hikey_bl2_handle_post_image_load(image_id);
183 }
184
reset_dwmmc_clk(void)185 static void reset_dwmmc_clk(void)
186 {
187 unsigned int data;
188
189 /* disable mmc0 bus clock */
190 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0);
191 do {
192 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
193 } while (data & PERI_CLK0_MMC0);
194 /* enable mmc0 bus clock */
195 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0);
196 do {
197 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
198 } while (!(data & PERI_CLK0_MMC0));
199 /* reset mmc0 clock domain */
200 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0);
201
202 /* bypass mmc0 clock phase */
203 data = mmio_read_32(PERI_SC_PERIPH_CTRL2);
204 data |= 3;
205 mmio_write_32(PERI_SC_PERIPH_CTRL2, data);
206
207 /* disable low power */
208 data = mmio_read_32(PERI_SC_PERIPH_CTRL13);
209 data |= 1 << 3;
210 mmio_write_32(PERI_SC_PERIPH_CTRL13, data);
211 do {
212 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
213 } while (!(data & PERI_RST0_MMC0));
214
215 /* unreset mmc0 clock domain */
216 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0);
217 do {
218 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
219 } while (data & PERI_RST0_MMC0);
220 }
221
hikey_boardid_init(void)222 static void hikey_boardid_init(void)
223 {
224 u_register_t midr;
225
226 midr = read_midr();
227 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr);
228 INFO("[BDID] [%x] midr: 0x%x\n", MEMORY_AXI_CHIP_ADDR,
229 (unsigned int)midr);
230
231 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0);
232 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b);
233
234 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234);
235 mmio_write_32(ACPU_ARM64_FLAGB, 0x5678);
236 }
237
hikey_sd_init(void)238 static void hikey_sd_init(void)
239 {
240 /* switch pinmux to SD */
241 mmio_write_32(IOMG_SD_CLK, IOMG_MUX_FUNC0);
242 mmio_write_32(IOMG_SD_CMD, IOMG_MUX_FUNC0);
243 mmio_write_32(IOMG_SD_DATA0, IOMG_MUX_FUNC0);
244 mmio_write_32(IOMG_SD_DATA1, IOMG_MUX_FUNC0);
245 mmio_write_32(IOMG_SD_DATA2, IOMG_MUX_FUNC0);
246 mmio_write_32(IOMG_SD_DATA3, IOMG_MUX_FUNC0);
247
248 mmio_write_32(IOCG_SD_CLK, IOCG_INPUT_16MA);
249 mmio_write_32(IOCG_SD_CMD, IOCG_INPUT_12MA);
250 mmio_write_32(IOCG_SD_DATA0, IOCG_INPUT_12MA);
251 mmio_write_32(IOCG_SD_DATA1, IOCG_INPUT_12MA);
252 mmio_write_32(IOCG_SD_DATA2, IOCG_INPUT_12MA);
253 mmio_write_32(IOCG_SD_DATA3, IOCG_INPUT_12MA);
254
255 /* set SD Card detect as nopull */
256 mmio_write_32(IOCG_GPIO8, 0);
257 }
258
hikey_jumper_init(void)259 static void hikey_jumper_init(void)
260 {
261 /* set jumper detect as nopull */
262 mmio_write_32(IOCG_GPIO24, 0);
263 /* set jumper detect as GPIO */
264 mmio_write_32(IOMG_GPIO24, IOMG_MUX_FUNC0);
265 }
266
bl2_el3_early_platform_setup(u_register_t arg1,u_register_t arg2,u_register_t arg3,u_register_t arg4)267 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
268 u_register_t arg3, u_register_t arg4)
269 {
270 /* Initialize the console to provide early debug support */
271 console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ,
272 PL011_BAUDRATE, &console);
273 /*
274 * Allow BL2 to see the whole Trusted RAM.
275 */
276 bl2_el3_tzram_layout.total_base = BL2_RW_BASE;
277 bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE;
278 }
279
bl2_el3_plat_arch_setup(void)280 void bl2_el3_plat_arch_setup(void)
281 {
282 hikey_init_mmu_el3(bl2_el3_tzram_layout.total_base,
283 bl2_el3_tzram_layout.total_size,
284 BL_CODE_BASE,
285 BL_CODE_END,
286 BL_COHERENT_RAM_BASE,
287 BL_COHERENT_RAM_END);
288 }
289
bl2_platform_setup(void)290 void bl2_platform_setup(void)
291 {
292 dw_mmc_params_t params;
293 struct mmc_device_info info;
294
295 hikey_sp804_init();
296 hikey_gpio_init();
297 hikey_pmussi_init();
298 hikey_hi6553_init();
299 /* Clear SRAM since it'll be used by MCU right now. */
300 memset((void *)SRAM_BASE, 0, SRAM_SIZE);
301
302 dsb();
303 hikey_ddr_init(DDR_FREQ_800M);
304 hikey_security_setup();
305
306 hikey_boardid_init();
307 init_acpu_dvfs();
308 hikey_rtc_init();
309 hikey_sd_init();
310 hikey_jumper_init();
311
312 hikey_mmc_pll_init();
313
314 /* Clean SRAM before MCU used */
315 clean_dcache_range(SRAM_BASE, SRAM_SIZE);
316
317 reset_dwmmc_clk();
318 memset(¶ms, 0, sizeof(dw_mmc_params_t));
319 params.reg_base = DWMMC0_BASE;
320 params.desc_base = HIKEY_MMC_DESC_BASE;
321 params.desc_size = 1 << 20;
322 params.clk_rate = 24 * 1000 * 1000;
323 params.bus_width = MMC_BUS_WIDTH_8;
324 params.flags = MMC_FLAG_CMD23;
325 info.mmc_dev_type = MMC_IS_EMMC;
326 dw_mmc_init(¶ms, &info);
327
328 hikey_io_setup();
329 }
330