1 /*
2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <stddef.h>
10 #include <string.h>
11
12 #include <platform_def.h>
13
14 #include <arch.h>
15 #include <arch_helpers.h>
16 #include <bl31/bl31.h>
17 #include <common/bl_common.h>
18 #include <common/debug.h>
19 #include <cortex_a53.h>
20 #include <drivers/arm/pl011.h>
21 #include <drivers/generic_delay_timer.h>
22 #include <lib/mmio.h>
23 #include <plat/common/platform.h>
24
25 #include "hi3798cv200.h"
26 #include "plat_private.h"
27
28 #define TZPC_SEC_ATTR_CTRL_VALUE (0x9DB98D45)
29
30 static entry_point_info_t bl32_image_ep_info;
31 static entry_point_info_t bl33_image_ep_info;
32 static console_t console;
33
hisi_tzpc_sec_init(void)34 static void hisi_tzpc_sec_init(void)
35 {
36 mmio_write_32(HISI_TZPC_SEC_ATTR_CTRL, TZPC_SEC_ATTR_CTRL_VALUE);
37 }
38
bl31_plat_get_next_image_ep_info(uint32_t type)39 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
40 {
41 entry_point_info_t *next_image_info;
42
43 assert(sec_state_is_valid(type));
44 next_image_info = (type == NON_SECURE)
45 ? &bl33_image_ep_info : &bl32_image_ep_info;
46 /*
47 * None of the images on the ARM development platforms can have 0x0
48 * as the entrypoint
49 */
50 if (next_image_info->pc)
51 return next_image_info;
52 else
53 return NULL;
54 }
55
56 /*******************************************************************************
57 * Perform any BL31 early platform setup common to ARM standard platforms.
58 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
59 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be
60 * done before the MMU is initialized so that the memory layout can be used
61 * while creating page tables. BL2 has flushed this information to memory, so
62 * we are guaranteed to pick up good data.
63 ******************************************************************************/
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)64 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
65 u_register_t arg2, u_register_t arg3)
66 {
67 void *from_bl2;
68
69 from_bl2 = (void *) arg0;
70
71 console_pl011_register(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ,
72 PL011_BAUDRATE, &console);
73
74 /* Init console for crash report */
75 plat_crash_console_init();
76
77 /*
78 * Check params passed from BL2 should not be NULL,
79 */
80 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
81
82 assert(params_from_bl2 != NULL);
83 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
84 assert(params_from_bl2->h.version >= VERSION_2);
85
86 bl_params_node_t *bl_params = params_from_bl2->head;
87
88 /*
89 * Copy BL33 and BL32 (if present), entry point information.
90 * They are stored in Secure RAM, in BL2's address space.
91 */
92 while (bl_params) {
93 if (bl_params->image_id == BL32_IMAGE_ID)
94 bl32_image_ep_info = *bl_params->ep_info;
95
96 if (bl_params->image_id == BL33_IMAGE_ID)
97 bl33_image_ep_info = *bl_params->ep_info;
98
99 bl_params = bl_params->next_params_info;
100 }
101
102 if (bl33_image_ep_info.pc == 0)
103 panic();
104 }
105
bl31_platform_setup(void)106 void bl31_platform_setup(void)
107 {
108 /* Init arch timer */
109 generic_delay_timer_init();
110
111 /* Init GIC distributor and CPU interface */
112 poplar_gic_driver_init();
113 poplar_gic_init();
114
115 /* Init security properties of IP blocks */
116 hisi_tzpc_sec_init();
117 }
118
bl31_plat_runtime_setup(void)119 void bl31_plat_runtime_setup(void)
120 {
121 /* do nothing */
122 }
123
bl31_plat_arch_setup(void)124 void bl31_plat_arch_setup(void)
125 {
126 plat_configure_mmu_el3(BL31_BASE,
127 (BL31_LIMIT - BL31_BASE),
128 BL_CODE_BASE,
129 BL_CODE_END,
130 BL_COHERENT_RAM_BASE,
131 BL_COHERENT_RAM_END);
132
133 INFO("Boot BL33 from 0x%lx for %llu Bytes\n",
134 bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2);
135 }
136