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1 /*
2  * Copyright © 2016 Red Hat.
3  * Copyright © 2016 Bas Nieuwenhuizen
4  *
5  * Based on radeon_winsys.h which is:
6  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
7  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
8  *
9  * Permission is hereby granted, free of charge, to any person obtaining a
10  * copy of this software and associated documentation files (the "Software"),
11  * to deal in the Software without restriction, including without limitation
12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13  * and/or sell copies of the Software, and to permit persons to whom the
14  * Software is furnished to do so, subject to the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the next
17  * paragraph) shall be included in all copies or substantial portions of the
18  * Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26  * IN THE SOFTWARE.
27  */
28 
29 #ifndef RADV_RADEON_WINSYS_H
30 #define RADV_RADEON_WINSYS_H
31 
32 #include <stdio.h>
33 #include <stdint.h>
34 #include <stdbool.h>
35 #include <stdlib.h>
36 #include <string.h>
37 #include <vulkan/vulkan.h>
38 #include "amd_family.h"
39 #include "util/u_memory.h"
40 #include "util/u_math.h"
41 
42 struct radeon_info;
43 struct ac_surf_info;
44 struct radeon_surf;
45 
46 enum radeon_bo_domain { /* bitfield */
47 	RADEON_DOMAIN_GTT  = 2,
48 	RADEON_DOMAIN_VRAM = 4,
49 	RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT,
50 	RADEON_DOMAIN_GDS = 8,
51 	RADEON_DOMAIN_OA = 16,
52 };
53 
54 enum radeon_bo_flag { /* bitfield */
55 	RADEON_FLAG_GTT_WC =        (1 << 0),
56 	RADEON_FLAG_CPU_ACCESS =    (1 << 1),
57 	RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
58 	RADEON_FLAG_VIRTUAL =       (1 << 3),
59 	RADEON_FLAG_VA_UNCACHED =   (1 << 4),
60 	RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
61 	RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
62 	RADEON_FLAG_READ_ONLY =     (1 << 7),
63 	RADEON_FLAG_32BIT =         (1 << 8),
64 	RADEON_FLAG_PREFER_LOCAL_BO = (1 << 9),
65 	RADEON_FLAG_ZERO_VRAM = (1 << 10),
66 };
67 
68 enum radeon_bo_usage { /* bitfield */
69 	RADEON_USAGE_READ = 2,
70 	RADEON_USAGE_WRITE = 4,
71 	RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
72 };
73 
74 enum radeon_ctx_priority {
75 	RADEON_CTX_PRIORITY_INVALID = -1,
76 	RADEON_CTX_PRIORITY_LOW = 0,
77 	RADEON_CTX_PRIORITY_MEDIUM,
78 	RADEON_CTX_PRIORITY_HIGH,
79 	RADEON_CTX_PRIORITY_REALTIME,
80 };
81 
82 enum radeon_value_id {
83 	RADEON_ALLOCATED_VRAM,
84 	RADEON_ALLOCATED_VRAM_VIS,
85 	RADEON_ALLOCATED_GTT,
86 	RADEON_TIMESTAMP,
87 	RADEON_NUM_BYTES_MOVED,
88 	RADEON_NUM_EVICTIONS,
89 	RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
90 	RADEON_VRAM_USAGE,
91 	RADEON_VRAM_VIS_USAGE,
92 	RADEON_GTT_USAGE,
93 	RADEON_GPU_TEMPERATURE,
94 	RADEON_CURRENT_SCLK,
95 	RADEON_CURRENT_MCLK,
96 };
97 
98 struct radeon_cmdbuf {
99 	unsigned cdw;  /* Number of used dwords. */
100 	unsigned max_dw; /* Maximum number of dwords. */
101 	uint32_t *buf; /* The base pointer of the chunk. */
102 };
103 
104 #define RADEON_SURF_TYPE_MASK                   0xFF
105 #define RADEON_SURF_TYPE_SHIFT                  0
106 #define     RADEON_SURF_TYPE_1D                     0
107 #define     RADEON_SURF_TYPE_2D                     1
108 #define     RADEON_SURF_TYPE_3D                     2
109 #define     RADEON_SURF_TYPE_CUBEMAP                3
110 #define     RADEON_SURF_TYPE_1D_ARRAY               4
111 #define     RADEON_SURF_TYPE_2D_ARRAY               5
112 #define RADEON_SURF_MODE_MASK                   0xFF
113 #define RADEON_SURF_MODE_SHIFT                  8
114 
115 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
116 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
117 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
118 
119 enum radeon_bo_layout {
120 	RADEON_LAYOUT_LINEAR = 0,
121 	RADEON_LAYOUT_TILED,
122 	RADEON_LAYOUT_SQUARETILED,
123 
124 	RADEON_LAYOUT_UNKNOWN
125 };
126 
127 /* Tiling info for display code, DRI sharing, and other data. */
128 struct radeon_bo_metadata {
129 	/* Tiling flags describing the texture layout for display code
130 	 * and DRI sharing.
131 	 */
132 	union {
133 		struct {
134 			enum radeon_bo_layout   microtile;
135 			enum radeon_bo_layout   macrotile;
136 			unsigned                pipe_config;
137 			unsigned                bankw;
138 			unsigned                bankh;
139 			unsigned                tile_split;
140 			unsigned                mtilea;
141 			unsigned                num_banks;
142 			unsigned                stride;
143 			bool                    scanout;
144 		} legacy;
145 
146 		struct {
147 			/* surface flags */
148 			unsigned swizzle_mode:5;
149 			bool scanout;
150 		} gfx9;
151 	} u;
152 
153 	/* Additional metadata associated with the buffer, in bytes.
154 	 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
155 	 * Supported by amdgpu only.
156 	 */
157 	uint32_t                size_metadata;
158 	uint32_t                metadata[64];
159 };
160 
161 struct radeon_winsys_fence;
162 struct radeon_winsys_ctx;
163 
164 struct radeon_winsys_bo {
165 	uint64_t va;
166 	bool is_local;
167 	bool vram_no_cpu_access;
168 };
169 struct radv_winsys_sem_counts {
170 	uint32_t syncobj_count;
171 	uint32_t syncobj_reset_count; /* for wait only, whether to reset the syncobj */
172 	uint32_t timeline_syncobj_count;
173 	uint32_t sem_count;
174 	uint32_t *syncobj;
175 	uint64_t *points;
176 	struct radeon_winsys_sem **sem;
177 };
178 
179 struct radv_winsys_sem_info {
180 	bool cs_emit_signal;
181 	bool cs_emit_wait;
182 	struct radv_winsys_sem_counts wait;
183 	struct radv_winsys_sem_counts signal;
184 };
185 
186 struct radv_winsys_bo_list {
187 	struct radeon_winsys_bo **bos;
188 	unsigned count;
189 };
190 
191 /* Kernel effectively allows 0-31. This sets some priorities for fixed
192  * functionality buffers */
193 enum {
194 	RADV_BO_PRIORITY_APPLICATION_MAX = 28,
195 
196 	/* virtual buffers have 0 priority since the priority is not used. */
197 	RADV_BO_PRIORITY_VIRTUAL = 0,
198 
199 	/* This should be considerably lower than most of the stuff below,
200 	 * but how much lower is hard to say since we don't know application
201 	 * assignments. Put it pretty high since it is GTT anyway. */
202 	RADV_BO_PRIORITY_QUERY_POOL = 29,
203 
204 	RADV_BO_PRIORITY_DESCRIPTOR = 30,
205 	RADV_BO_PRIORITY_UPLOAD_BUFFER = 30,
206 	RADV_BO_PRIORITY_FENCE = 30,
207 	RADV_BO_PRIORITY_SHADER = 31,
208 	RADV_BO_PRIORITY_SCRATCH = 31,
209 	RADV_BO_PRIORITY_CS = 31,
210 };
211 
212 struct radeon_winsys {
213 	void (*destroy)(struct radeon_winsys *ws);
214 
215 	void (*query_info)(struct radeon_winsys *ws,
216 			   struct radeon_info *info);
217 
218 	uint64_t (*query_value)(struct radeon_winsys *ws,
219 				enum radeon_value_id value);
220 
221 	bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
222 			       unsigned num_registers, uint32_t *out);
223 
224 	const char *(*get_chip_name)(struct radeon_winsys *ws);
225 
226 	struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
227 						  uint64_t size,
228 						  unsigned alignment,
229 						  enum radeon_bo_domain domain,
230 						  enum radeon_bo_flag flags,
231 						  unsigned priority);
232 
233 	void (*buffer_destroy)(struct radeon_winsys_bo *bo);
234 	void *(*buffer_map)(struct radeon_winsys_bo *bo);
235 
236 	struct radeon_winsys_bo *(*buffer_from_ptr)(struct radeon_winsys *ws,
237 						    void *pointer,
238 						    uint64_t size,
239 						    unsigned priority);
240 
241 	struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
242 						   int fd,
243 						   unsigned priority,
244 						   uint64_t *alloc_size);
245 
246 	bool (*buffer_get_fd)(struct radeon_winsys *ws,
247 			      struct radeon_winsys_bo *bo,
248 			      int *fd);
249 
250 	bool (*buffer_get_flags_from_fd)(struct radeon_winsys *ws, int fd,
251 	                                 enum radeon_bo_domain *domains,
252 	                                 enum radeon_bo_flag *flags);
253 
254 	void (*buffer_unmap)(struct radeon_winsys_bo *bo);
255 
256 	void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
257 				    struct radeon_bo_metadata *md);
258 	void (*buffer_get_metadata)(struct radeon_winsys_bo *bo,
259 				    struct radeon_bo_metadata *md);
260 
261 	VkResult (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
262 					uint64_t offset, uint64_t size,
263 					struct radeon_winsys_bo *bo, uint64_t bo_offset);
264 	VkResult (*ctx_create)(struct radeon_winsys *ws,
265 	                       enum radeon_ctx_priority priority,
266 	                       struct radeon_winsys_ctx **ctx);
267 	void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
268 
269 	bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
270 	                      enum ring_type ring_type, int ring_index);
271 
272 	struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws,
273 					      enum ring_type ring_type);
274 
275 	void (*cs_destroy)(struct radeon_cmdbuf *cs);
276 
277 	void (*cs_reset)(struct radeon_cmdbuf *cs);
278 
279 	VkResult (*cs_finalize)(struct radeon_cmdbuf *cs);
280 
281 	void (*cs_grow)(struct radeon_cmdbuf * cs, size_t min_size);
282 
283 	VkResult (*cs_submit)(struct radeon_winsys_ctx *ctx,
284 			      int queue_index,
285 			      struct radeon_cmdbuf **cs_array,
286 			      unsigned cs_count,
287 			      struct radeon_cmdbuf *initial_preamble_cs,
288 			      struct radeon_cmdbuf *continue_preamble_cs,
289 			      struct radv_winsys_sem_info *sem_info,
290 			      const struct radv_winsys_bo_list *bo_list, /* optional */
291 			      bool can_patch,
292 			      struct radeon_winsys_fence *fence);
293 
294 	void (*cs_add_buffer)(struct radeon_cmdbuf *cs,
295 			      struct radeon_winsys_bo *bo);
296 
297 	void (*cs_execute_secondary)(struct radeon_cmdbuf *parent,
298 				    struct radeon_cmdbuf *child);
299 
300 	void (*cs_dump)(struct radeon_cmdbuf *cs, FILE* file, const int *trace_ids, int trace_id_count);
301 
302 	int (*surface_init)(struct radeon_winsys *ws,
303 			    const struct ac_surf_info *surf_info,
304 			    struct radeon_surf *surf);
305 
306 	struct radeon_winsys_fence *(*create_fence)();
307 	void (*destroy_fence)(struct radeon_winsys_fence *fence);
308 	void (*reset_fence)(struct radeon_winsys_fence *fence);
309 	void (*signal_fence)(struct radeon_winsys_fence *fence);
310 	bool (*is_fence_waitable)(struct radeon_winsys_fence *fence);
311 	bool (*fence_wait)(struct radeon_winsys *ws,
312 			   struct radeon_winsys_fence *fence,
313 			   bool absolute,
314 			   uint64_t timeout);
315 	bool (*fences_wait)(struct radeon_winsys *ws,
316 			    struct radeon_winsys_fence *const *fences,
317 			    uint32_t fence_count,
318 			    bool wait_all,
319 			    uint64_t timeout);
320 
321 	/* old semaphores - non shareable */
322 	struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
323 	void (*destroy_sem)(struct radeon_winsys_sem *sem);
324 
325 	/* new shareable sync objects */
326 	int (*create_syncobj)(struct radeon_winsys *ws, bool create_signaled,
327 			      uint32_t *handle);
328 	void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
329 
330 	void (*reset_syncobj)(struct radeon_winsys *ws, uint32_t handle);
331 	void (*signal_syncobj)(struct radeon_winsys *ws, uint32_t handle, uint64_t point);
332 	VkResult (*query_syncobj)(struct radeon_winsys *ws, uint32_t handle, uint64_t *point);
333 	bool (*wait_syncobj)(struct radeon_winsys *ws, const uint32_t *handles, uint32_t handle_count,
334 			     bool wait_all, uint64_t timeout);
335 	bool (*wait_timeline_syncobj)(struct radeon_winsys *ws, const uint32_t *handles, const uint64_t *points,
336 	                              uint32_t handle_count, bool wait_all, bool available, uint64_t timeout);
337 
338 	int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
339 	int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj);
340 
341 	int (*export_syncobj_to_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
342 
343 	/* Note that this, unlike the normal import, uses an existing syncobj. */
344 	int (*import_syncobj_from_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int fd);
345 
346 };
347 
radeon_emit(struct radeon_cmdbuf * cs,uint32_t value)348 static inline void radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
349 {
350 	cs->buf[cs->cdw++] = value;
351 }
352 
radeon_emit_array(struct radeon_cmdbuf * cs,const uint32_t * values,unsigned count)353 static inline void radeon_emit_array(struct radeon_cmdbuf *cs,
354 				     const uint32_t *values, unsigned count)
355 {
356 	memcpy(cs->buf + cs->cdw, values, count * 4);
357 	cs->cdw += count;
358 }
359 
radv_buffer_get_va(struct radeon_winsys_bo * bo)360 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo)
361 {
362 	return bo->va;
363 }
364 
radv_cs_add_buffer(struct radeon_winsys * ws,struct radeon_cmdbuf * cs,struct radeon_winsys_bo * bo)365 static inline void radv_cs_add_buffer(struct radeon_winsys *ws,
366 				      struct radeon_cmdbuf *cs,
367 				      struct radeon_winsys_bo *bo)
368 {
369 	if (bo->is_local)
370 		return;
371 
372 	ws->cs_add_buffer(cs, bo);
373 }
374 
375 #endif /* RADV_RADEON_WINSYS_H */
376