1 /*
2 * Copyright © 2017 Red Hat
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23 #include "radv_private.h"
24 #include "radv_shader.h"
25 #include "nir/nir.h"
26 #include "nir/nir_xfb_info.h"
27
mark_sampler_desc(const nir_variable * var,struct radv_shader_info * info)28 static void mark_sampler_desc(const nir_variable *var,
29 struct radv_shader_info *info)
30 {
31 info->desc_set_used_mask |= (1u << var->data.descriptor_set);
32 }
33
34 static void
gather_intrinsic_load_input_info(const nir_shader * nir,const nir_intrinsic_instr * instr,struct radv_shader_info * info)35 gather_intrinsic_load_input_info(const nir_shader *nir,
36 const nir_intrinsic_instr *instr,
37 struct radv_shader_info *info)
38 {
39 switch (nir->info.stage) {
40 case MESA_SHADER_VERTEX: {
41 unsigned idx = nir_intrinsic_io_semantics(instr).location;
42 unsigned component = nir_intrinsic_component(instr);
43 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
44
45 info->vs.input_usage_mask[idx] |= mask << component;
46 break;
47 }
48 default:
49 break;
50 }
51 }
52
53 static uint32_t
widen_writemask(uint32_t wrmask)54 widen_writemask(uint32_t wrmask)
55 {
56 uint32_t new_wrmask = 0;
57 for(unsigned i = 0; i < 4; i++)
58 new_wrmask |= (wrmask & (1 << i) ? 0x3 : 0x0) << (i * 2);
59 return new_wrmask;
60 }
61
62 static void
set_writes_memory(const nir_shader * nir,struct radv_shader_info * info)63 set_writes_memory(const nir_shader *nir, struct radv_shader_info *info)
64 {
65 if (nir->info.stage == MESA_SHADER_FRAGMENT)
66 info->ps.writes_memory = true;
67 }
68
69 static void
gather_intrinsic_store_output_info(const nir_shader * nir,const nir_intrinsic_instr * instr,struct radv_shader_info * info)70 gather_intrinsic_store_output_info(const nir_shader *nir,
71 const nir_intrinsic_instr *instr,
72 struct radv_shader_info *info)
73 {
74 unsigned idx = nir_intrinsic_base(instr);
75 unsigned num_slots = nir_intrinsic_io_semantics(instr).num_slots;
76 unsigned component = nir_intrinsic_component(instr);
77 unsigned write_mask = nir_intrinsic_write_mask(instr);
78 uint8_t *output_usage_mask = NULL;
79
80 if (instr->src[0].ssa->bit_size == 64)
81 write_mask = widen_writemask(write_mask);
82
83 switch (nir->info.stage) {
84 case MESA_SHADER_VERTEX:
85 output_usage_mask = info->vs.output_usage_mask;
86 break;
87 case MESA_SHADER_TESS_EVAL:
88 output_usage_mask = info->tes.output_usage_mask;
89 break;
90 case MESA_SHADER_GEOMETRY:
91 output_usage_mask = info->gs.output_usage_mask;
92 break;
93 default:
94 break;
95 }
96
97 if (output_usage_mask) {
98 for (unsigned i = 0; i < num_slots; i++) {
99 output_usage_mask[idx + i] |=
100 ((write_mask >> (i * 4)) & 0xf) << component;
101 }
102 }
103 }
104
105 static void
gather_push_constant_info(const nir_shader * nir,const nir_intrinsic_instr * instr,struct radv_shader_info * info)106 gather_push_constant_info(const nir_shader *nir,
107 const nir_intrinsic_instr *instr,
108 struct radv_shader_info *info)
109 {
110 int base = nir_intrinsic_base(instr);
111
112 if (!nir_src_is_const(instr->src[0])) {
113 info->has_indirect_push_constants = true;
114 } else {
115 uint32_t min = base + nir_src_as_uint(instr->src[0]);
116 uint32_t max = min + instr->num_components * 4;
117
118 info->max_push_constant_used =
119 MAX2(max, info->max_push_constant_used);
120 info->min_push_constant_used =
121 MIN2(min, info->min_push_constant_used);
122 }
123
124 if (instr->dest.ssa.bit_size != 32)
125 info->has_only_32bit_push_constants = false;
126
127 info->loads_push_constants = true;
128 }
129
130 static void
gather_intrinsic_info(const nir_shader * nir,const nir_intrinsic_instr * instr,struct radv_shader_info * info)131 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
132 struct radv_shader_info *info)
133 {
134 switch (instr->intrinsic) {
135 case nir_intrinsic_load_barycentric_at_sample:
136 info->ps.needs_sample_positions = true;
137 break;
138 case nir_intrinsic_load_draw_id:
139 info->vs.needs_draw_id = true;
140 break;
141 case nir_intrinsic_load_instance_id:
142 info->vs.needs_instance_id = true;
143 break;
144 case nir_intrinsic_load_num_work_groups:
145 info->cs.uses_grid_size = true;
146 break;
147 case nir_intrinsic_load_local_invocation_id:
148 case nir_intrinsic_load_work_group_id: {
149 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
150 while (mask) {
151 unsigned i = u_bit_scan(&mask);
152
153 if (instr->intrinsic == nir_intrinsic_load_work_group_id)
154 info->cs.uses_block_id[i] = true;
155 else
156 info->cs.uses_thread_id[i] = true;
157 }
158 break;
159 }
160 case nir_intrinsic_load_local_invocation_index:
161 case nir_intrinsic_load_subgroup_id:
162 case nir_intrinsic_load_num_subgroups:
163 info->cs.uses_local_invocation_idx = true;
164 break;
165 case nir_intrinsic_load_sample_id:
166 info->ps.force_persample = true;
167 break;
168 case nir_intrinsic_load_sample_pos:
169 info->ps.force_persample = true;
170 break;
171 case nir_intrinsic_load_view_index:
172 info->needs_multiview_view_index = true;
173 if (nir->info.stage == MESA_SHADER_FRAGMENT)
174 info->ps.layer_input = true;
175 break;
176 case nir_intrinsic_load_layer_id:
177 if (nir->info.stage == MESA_SHADER_FRAGMENT)
178 info->ps.layer_input = true;
179 break;
180 case nir_intrinsic_load_invocation_id:
181 info->uses_invocation_id = true;
182 break;
183 case nir_intrinsic_load_primitive_id:
184 info->uses_prim_id = true;
185 break;
186 case nir_intrinsic_load_push_constant:
187 gather_push_constant_info(nir, instr, info);
188 break;
189 case nir_intrinsic_vulkan_resource_index:
190 info->desc_set_used_mask |= (1u << nir_intrinsic_desc_set(instr));
191 break;
192 case nir_intrinsic_image_deref_load:
193 case nir_intrinsic_image_deref_store:
194 case nir_intrinsic_image_deref_atomic_add:
195 case nir_intrinsic_image_deref_atomic_imin:
196 case nir_intrinsic_image_deref_atomic_umin:
197 case nir_intrinsic_image_deref_atomic_imax:
198 case nir_intrinsic_image_deref_atomic_umax:
199 case nir_intrinsic_image_deref_atomic_and:
200 case nir_intrinsic_image_deref_atomic_or:
201 case nir_intrinsic_image_deref_atomic_xor:
202 case nir_intrinsic_image_deref_atomic_exchange:
203 case nir_intrinsic_image_deref_atomic_comp_swap:
204 case nir_intrinsic_image_deref_size: {
205 nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
206 mark_sampler_desc(var, info);
207
208 if (instr->intrinsic == nir_intrinsic_image_deref_store ||
209 instr->intrinsic == nir_intrinsic_image_deref_atomic_add ||
210 instr->intrinsic == nir_intrinsic_image_deref_atomic_imin ||
211 instr->intrinsic == nir_intrinsic_image_deref_atomic_umin ||
212 instr->intrinsic == nir_intrinsic_image_deref_atomic_imax ||
213 instr->intrinsic == nir_intrinsic_image_deref_atomic_umax ||
214 instr->intrinsic == nir_intrinsic_image_deref_atomic_and ||
215 instr->intrinsic == nir_intrinsic_image_deref_atomic_or ||
216 instr->intrinsic == nir_intrinsic_image_deref_atomic_xor ||
217 instr->intrinsic == nir_intrinsic_image_deref_atomic_exchange ||
218 instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap) {
219 set_writes_memory(nir, info);
220 }
221 break;
222 }
223 case nir_intrinsic_store_ssbo:
224 case nir_intrinsic_ssbo_atomic_add:
225 case nir_intrinsic_ssbo_atomic_imin:
226 case nir_intrinsic_ssbo_atomic_umin:
227 case nir_intrinsic_ssbo_atomic_imax:
228 case nir_intrinsic_ssbo_atomic_umax:
229 case nir_intrinsic_ssbo_atomic_and:
230 case nir_intrinsic_ssbo_atomic_or:
231 case nir_intrinsic_ssbo_atomic_xor:
232 case nir_intrinsic_ssbo_atomic_exchange:
233 case nir_intrinsic_ssbo_atomic_comp_swap:
234 case nir_intrinsic_store_global:
235 case nir_intrinsic_global_atomic_add:
236 case nir_intrinsic_global_atomic_imin:
237 case nir_intrinsic_global_atomic_umin:
238 case nir_intrinsic_global_atomic_imax:
239 case nir_intrinsic_global_atomic_umax:
240 case nir_intrinsic_global_atomic_and:
241 case nir_intrinsic_global_atomic_or:
242 case nir_intrinsic_global_atomic_xor:
243 case nir_intrinsic_global_atomic_exchange:
244 case nir_intrinsic_global_atomic_comp_swap:
245 set_writes_memory(nir, info);
246 break;
247 case nir_intrinsic_load_input:
248 gather_intrinsic_load_input_info(nir, instr, info);
249 break;
250 case nir_intrinsic_store_output:
251 gather_intrinsic_store_output_info(nir, instr, info);
252 break;
253 default:
254 break;
255 }
256 }
257
258 static void
gather_tex_info(const nir_shader * nir,const nir_tex_instr * instr,struct radv_shader_info * info)259 gather_tex_info(const nir_shader *nir, const nir_tex_instr *instr,
260 struct radv_shader_info *info)
261 {
262 for (unsigned i = 0; i < instr->num_srcs; i++) {
263 switch (instr->src[i].src_type) {
264 case nir_tex_src_texture_deref:
265 mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info);
266 break;
267 case nir_tex_src_sampler_deref:
268 mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info);
269 break;
270 default:
271 break;
272 }
273 }
274 }
275
276 static void
gather_info_block(const nir_shader * nir,const nir_block * block,struct radv_shader_info * info)277 gather_info_block(const nir_shader *nir, const nir_block *block,
278 struct radv_shader_info *info)
279 {
280 nir_foreach_instr(instr, block) {
281 switch (instr->type) {
282 case nir_instr_type_intrinsic:
283 gather_intrinsic_info(nir, nir_instr_as_intrinsic(instr), info);
284 break;
285 case nir_instr_type_tex:
286 gather_tex_info(nir, nir_instr_as_tex(instr), info);
287 break;
288 default:
289 break;
290 }
291 }
292 }
293
294 static void
gather_info_input_decl_vs(const nir_shader * nir,const nir_variable * var,struct radv_shader_info * info,const struct radv_shader_variant_key * key)295 gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var,
296 struct radv_shader_info *info,
297 const struct radv_shader_variant_key *key)
298 {
299 unsigned attrib_count = glsl_count_attribute_slots(var->type, true);
300 int idx = var->data.location;
301
302 if (idx >= VERT_ATTRIB_GENERIC0 && idx < VERT_ATTRIB_GENERIC0 + MAX_VERTEX_ATTRIBS)
303 info->vs.has_vertex_buffers = true;
304
305 for (unsigned i = 0; i < attrib_count; ++i) {
306 unsigned attrib_index = var->data.location + i - VERT_ATTRIB_GENERIC0;
307
308 if (key->vs.instance_rate_inputs & (1u << attrib_index))
309 info->vs.needs_instance_id = true;
310 }
311 }
312
313 static void
mark_16bit_ps_input(struct radv_shader_info * info,const struct glsl_type * type,int location)314 mark_16bit_ps_input(struct radv_shader_info *info, const struct glsl_type *type,
315 int location)
316 {
317 if (glsl_type_is_scalar(type) || glsl_type_is_vector(type) || glsl_type_is_matrix(type)) {
318 unsigned attrib_count = glsl_count_attribute_slots(type, false);
319 if (glsl_type_is_16bit(type)) {
320 info->ps.float16_shaded_mask |= ((1ull << attrib_count) - 1) << location;
321 }
322 } else if (glsl_type_is_array(type)) {
323 unsigned stride = glsl_count_attribute_slots(glsl_get_array_element(type), false);
324 for (unsigned i = 0; i < glsl_get_length(type); ++i) {
325 mark_16bit_ps_input(info, glsl_get_array_element(type), location + i * stride);
326 }
327 } else {
328 assert(glsl_type_is_struct_or_ifc(type));
329 for (unsigned i = 0; i < glsl_get_length(type); i++) {
330 mark_16bit_ps_input(info, glsl_get_struct_field(type, i), location);
331 location += glsl_count_attribute_slots(glsl_get_struct_field(type, i), false);
332 }
333 }
334 }
335 static void
gather_info_input_decl_ps(const nir_shader * nir,const nir_variable * var,struct radv_shader_info * info)336 gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
337 struct radv_shader_info *info)
338 {
339 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
340 const struct glsl_type *type = glsl_without_array(var->type);
341 int idx = var->data.location;
342
343 switch (idx) {
344 case VARYING_SLOT_PNTC:
345 info->ps.has_pcoord = true;
346 break;
347 case VARYING_SLOT_PRIMITIVE_ID:
348 info->ps.prim_id_input = true;
349 break;
350 case VARYING_SLOT_LAYER:
351 info->ps.layer_input = true;
352 break;
353 case VARYING_SLOT_CLIP_DIST0:
354 case VARYING_SLOT_CLIP_DIST1:
355 info->ps.num_input_clips_culls += attrib_count;
356 break;
357 case VARYING_SLOT_VIEWPORT:
358 info->ps.viewport_index_input = true;
359 break;
360 default:
361 break;
362 }
363
364 if (glsl_get_base_type(type) == GLSL_TYPE_FLOAT) {
365 if (var->data.sample)
366 info->ps.force_persample = true;
367 }
368
369 if (var->data.compact) {
370 unsigned component_count = var->data.location_frac +
371 glsl_get_length(var->type);
372 attrib_count = (component_count + 3) / 4;
373 } else {
374 mark_16bit_ps_input(info, var->type, var->data.driver_location);
375 }
376
377 uint64_t mask = ((1ull << attrib_count) - 1);
378
379 if (var->data.interpolation == INTERP_MODE_FLAT)
380 info->ps.flat_shaded_mask |= mask << var->data.driver_location;
381 if (var->data.interpolation == INTERP_MODE_EXPLICIT)
382 info->ps.explicit_shaded_mask |= mask << var->data.driver_location;
383
384 if (var->data.location >= VARYING_SLOT_VAR0)
385 info->ps.input_mask |= mask << (var->data.location - VARYING_SLOT_VAR0);
386 }
387
388 static void
gather_info_input_decl(const nir_shader * nir,const nir_variable * var,struct radv_shader_info * info,const struct radv_shader_variant_key * key)389 gather_info_input_decl(const nir_shader *nir, const nir_variable *var,
390 struct radv_shader_info *info,
391 const struct radv_shader_variant_key *key)
392 {
393 switch (nir->info.stage) {
394 case MESA_SHADER_VERTEX:
395 gather_info_input_decl_vs(nir, var, info, key);
396 break;
397 case MESA_SHADER_FRAGMENT:
398 gather_info_input_decl_ps(nir, var, info);
399 break;
400 default:
401 break;
402 }
403 }
404
405 static void
gather_info_output_decl_ps(const nir_shader * nir,const nir_variable * var,struct radv_shader_info * info)406 gather_info_output_decl_ps(const nir_shader *nir, const nir_variable *var,
407 struct radv_shader_info *info)
408 {
409 int idx = var->data.location;
410
411 switch (idx) {
412 case FRAG_RESULT_DEPTH:
413 info->ps.writes_z = true;
414 break;
415 case FRAG_RESULT_STENCIL:
416 info->ps.writes_stencil = true;
417 break;
418 case FRAG_RESULT_SAMPLE_MASK:
419 info->ps.writes_sample_mask = true;
420 break;
421 default:
422 break;
423 }
424
425 if (idx >= FRAG_RESULT_DATA0 && idx <= FRAG_RESULT_DATA7) {
426 unsigned num_components = glsl_get_component_slots(glsl_without_array(var->type));
427 unsigned num_slots = glsl_count_attribute_slots(var->type, false);
428 unsigned write_mask = (1 << num_components) - 1;
429 unsigned slot = idx - FRAG_RESULT_DATA0;
430
431 for (unsigned i = 0; i < num_slots; i++) {
432 info->ps.cb_shader_mask |= write_mask << ((slot + i) * 4);
433 }
434 }
435 }
436
437 static void
gather_info_output_decl_gs(const nir_shader * nir,const nir_variable * var,struct radv_shader_info * info)438 gather_info_output_decl_gs(const nir_shader *nir, const nir_variable *var,
439 struct radv_shader_info *info)
440 {
441 unsigned num_components = glsl_get_component_slots(var->type);
442 unsigned stream = var->data.stream;
443 unsigned idx = var->data.location;
444
445 assert(stream < 4);
446
447 info->gs.max_stream = MAX2(info->gs.max_stream, stream);
448 info->gs.num_stream_output_components[stream] += num_components;
449 info->gs.output_streams[idx] = stream;
450 }
451
452 static void
gather_info_output_decl(const nir_shader * nir,const nir_variable * var,struct radv_shader_info * info,const struct radv_shader_variant_key * key)453 gather_info_output_decl(const nir_shader *nir, const nir_variable *var,
454 struct radv_shader_info *info,
455 const struct radv_shader_variant_key *key)
456 {
457 struct radv_vs_output_info *vs_info = NULL;
458
459 switch (nir->info.stage) {
460 case MESA_SHADER_FRAGMENT:
461 gather_info_output_decl_ps(nir, var, info);
462 break;
463 case MESA_SHADER_VERTEX:
464 if (!key->vs_common_out.as_ls &&
465 !key->vs_common_out.as_es)
466 vs_info = &info->vs.outinfo;
467
468 /* TODO: Adjust as_ls/as_nng. */
469 if (!key->vs_common_out.as_ls && key->vs_common_out.as_ngg)
470 gather_info_output_decl_gs(nir, var, info);
471 break;
472 case MESA_SHADER_GEOMETRY:
473 vs_info = &info->vs.outinfo;
474 gather_info_output_decl_gs(nir, var, info);
475 break;
476 case MESA_SHADER_TESS_EVAL:
477 if (!key->vs_common_out.as_es)
478 vs_info = &info->tes.outinfo;
479 break;
480 default:
481 break;
482 }
483
484 if (vs_info) {
485 switch (var->data.location) {
486 case VARYING_SLOT_CLIP_DIST0:
487 vs_info->clip_dist_mask =
488 (1 << nir->info.clip_distance_array_size) - 1;
489 vs_info->cull_dist_mask =
490 (1 << nir->info.cull_distance_array_size) - 1;
491 vs_info->cull_dist_mask <<= nir->info.clip_distance_array_size;
492 break;
493 case VARYING_SLOT_PSIZ:
494 vs_info->writes_pointsize = true;
495 break;
496 case VARYING_SLOT_VIEWPORT:
497 vs_info->writes_viewport_index = true;
498 break;
499 case VARYING_SLOT_LAYER:
500 vs_info->writes_layer = true;
501 break;
502 default:
503 break;
504 }
505 }
506 }
507
508 static void
gather_xfb_info(const nir_shader * nir,struct radv_shader_info * info)509 gather_xfb_info(const nir_shader *nir, struct radv_shader_info *info)
510 {
511 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
512 struct radv_streamout_info *so = &info->so;
513
514 if (!xfb)
515 return;
516
517 assert(xfb->output_count < MAX_SO_OUTPUTS);
518 so->num_outputs = xfb->output_count;
519
520 for (unsigned i = 0; i < xfb->output_count; i++) {
521 struct radv_stream_output *output = &so->outputs[i];
522
523 output->buffer = xfb->outputs[i].buffer;
524 output->stream = xfb->buffer_to_stream[xfb->outputs[i].buffer];
525 output->offset = xfb->outputs[i].offset;
526 output->location = xfb->outputs[i].location;
527 output->component_mask = xfb->outputs[i].component_mask;
528
529 so->enabled_stream_buffers_mask |=
530 (1 << output->buffer) << (output->stream * 4);
531
532 }
533
534 for (unsigned i = 0; i < NIR_MAX_XFB_BUFFERS; i++) {
535 so->strides[i] = xfb->buffers[i].stride / 4;
536 }
537
538 ralloc_free(xfb);
539 }
540
541 void
radv_nir_shader_info_init(struct radv_shader_info * info)542 radv_nir_shader_info_init(struct radv_shader_info *info)
543 {
544 /* Assume that shaders only have 32-bit push constants by default. */
545 info->min_push_constant_used = UINT8_MAX;
546 info->has_only_32bit_push_constants = true;
547 }
548
549 void
radv_nir_shader_info_pass(const struct nir_shader * nir,const struct radv_pipeline_layout * layout,const struct radv_shader_variant_key * key,struct radv_shader_info * info)550 radv_nir_shader_info_pass(const struct nir_shader *nir,
551 const struct radv_pipeline_layout *layout,
552 const struct radv_shader_variant_key *key,
553 struct radv_shader_info *info)
554 {
555 struct nir_function *func =
556 (struct nir_function *)exec_list_get_head_const(&nir->functions);
557
558 if (layout && layout->dynamic_offset_count &&
559 (layout->dynamic_shader_stages & mesa_to_vk_shader_stage(nir->info.stage))) {
560 info->loads_push_constants = true;
561 info->loads_dynamic_offsets = true;
562 }
563
564 nir_foreach_shader_in_variable(variable, nir)
565 gather_info_input_decl(nir, variable, info, key);
566
567 nir_foreach_block(block, func->impl) {
568 gather_info_block(nir, block, info);
569 }
570
571 nir_foreach_shader_out_variable(variable, nir)
572 gather_info_output_decl(nir, variable, info, key);
573
574 if (nir->info.stage == MESA_SHADER_VERTEX ||
575 nir->info.stage == MESA_SHADER_TESS_EVAL ||
576 nir->info.stage == MESA_SHADER_GEOMETRY)
577 gather_xfb_info(nir, info);
578
579 /* Make sure to export the LayerID if the fragment shader needs it. */
580 if (key->vs_common_out.export_layer_id) {
581 switch (nir->info.stage) {
582 case MESA_SHADER_VERTEX:
583 info->vs.output_usage_mask[VARYING_SLOT_LAYER] |= 0x1;
584 break;
585 case MESA_SHADER_TESS_EVAL:
586 info->tes.output_usage_mask[VARYING_SLOT_LAYER] |= 0x1;
587 break;
588 case MESA_SHADER_GEOMETRY:
589 info->gs.output_usage_mask[VARYING_SLOT_LAYER] |= 0x1;
590 break;
591 default:
592 break;
593 }
594 }
595
596 /* Make sure to export the LayerID if the subpass has multiviews. */
597 if (key->has_multiview_view_index) {
598 switch (nir->info.stage) {
599 case MESA_SHADER_VERTEX:
600 info->vs.outinfo.writes_layer = true;
601 break;
602 case MESA_SHADER_TESS_EVAL:
603 info->tes.outinfo.writes_layer = true;
604 break;
605 case MESA_SHADER_GEOMETRY:
606 info->vs.outinfo.writes_layer = true;
607 break;
608 default:
609 break;
610 }
611 }
612
613 /* Make sure to export the PrimitiveID if the fragment shader needs it. */
614 if (key->vs_common_out.export_prim_id) {
615 switch (nir->info.stage) {
616 case MESA_SHADER_VERTEX:
617 info->vs.outinfo.export_prim_id = true;
618 break;
619 case MESA_SHADER_TESS_EVAL:
620 info->tes.outinfo.export_prim_id = true;
621 break;
622 case MESA_SHADER_GEOMETRY:
623 info->vs.outinfo.export_prim_id = true;
624 break;
625 default:
626 break;
627 }
628 }
629
630 /* Make sure to export the ViewportIndex if the fragment shader needs it. */
631 if (key->vs_common_out.export_viewport_index) {
632 switch (nir->info.stage) {
633 case MESA_SHADER_VERTEX:
634 info->vs.output_usage_mask[VARYING_SLOT_VIEWPORT] |= 0x1;
635 break;
636 case MESA_SHADER_TESS_EVAL:
637 info->tes.output_usage_mask[VARYING_SLOT_VIEWPORT] |= 0x1;
638 break;
639 case MESA_SHADER_GEOMETRY:
640 info->gs.output_usage_mask[VARYING_SLOT_VIEWPORT] |= 0x1;
641 break;
642 default:
643 break;
644 }
645 }
646
647 if (nir->info.stage == MESA_SHADER_FRAGMENT)
648 info->ps.num_interp = nir->num_inputs;
649
650 switch (nir->info.stage) {
651 case MESA_SHADER_COMPUTE:
652 for (int i = 0; i < 3; ++i)
653 info->cs.block_size[i] = nir->info.cs.local_size[i];
654 break;
655 case MESA_SHADER_FRAGMENT:
656 info->ps.can_discard = nir->info.fs.uses_discard;
657 info->ps.early_fragment_test = nir->info.fs.early_fragment_tests;
658 info->ps.post_depth_coverage = nir->info.fs.post_depth_coverage;
659 info->ps.depth_layout = nir->info.fs.depth_layout;
660 break;
661 case MESA_SHADER_GEOMETRY:
662 info->gs.vertices_in = nir->info.gs.vertices_in;
663 info->gs.vertices_out = nir->info.gs.vertices_out;
664 info->gs.output_prim = nir->info.gs.output_primitive;
665 info->gs.invocations = nir->info.gs.invocations;
666 break;
667 case MESA_SHADER_TESS_EVAL:
668 info->tes.primitive_mode = nir->info.tess.primitive_mode;
669 info->tes.spacing = nir->info.tess.spacing;
670 info->tes.ccw = nir->info.tess.ccw;
671 info->tes.point_mode = nir->info.tess.point_mode;
672 info->tes.as_es = key->vs_common_out.as_es;
673 info->tes.export_prim_id = key->vs_common_out.export_prim_id;
674 info->is_ngg = key->vs_common_out.as_ngg;
675 info->is_ngg_passthrough = key->vs_common_out.as_ngg_passthrough;
676 break;
677 case MESA_SHADER_TESS_CTRL:
678 info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
679 break;
680 case MESA_SHADER_VERTEX:
681 info->vs.as_es = key->vs_common_out.as_es;
682 info->vs.as_ls = key->vs_common_out.as_ls;
683 info->vs.export_prim_id = key->vs_common_out.export_prim_id;
684 info->is_ngg = key->vs_common_out.as_ngg;
685 info->is_ngg_passthrough = key->vs_common_out.as_ngg_passthrough;
686 break;
687 default:
688 break;
689 }
690
691 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
692 unsigned add_clip = nir->info.clip_distance_array_size +
693 nir->info.cull_distance_array_size > 4;
694 info->gs.gsvs_vertex_size =
695 (util_bitcount64(nir->info.outputs_written) + add_clip) * 16;
696 info->gs.max_gsvs_emit_size =
697 info->gs.gsvs_vertex_size * nir->info.gs.vertices_out;
698 }
699
700 /* Compute the ESGS item size for VS or TES as ES. */
701 if ((nir->info.stage == MESA_SHADER_VERTEX ||
702 nir->info.stage == MESA_SHADER_TESS_EVAL) &&
703 key->vs_common_out.as_es) {
704 struct radv_es_output_info *es_info =
705 nir->info.stage == MESA_SHADER_VERTEX ? &info->vs.es_info : &info->tes.es_info;
706 uint32_t num_outputs_written = nir->info.stage == MESA_SHADER_VERTEX
707 ? info->vs.num_linked_outputs
708 : info->tes.num_linked_outputs;
709 es_info->esgs_itemsize = num_outputs_written * 16;
710 }
711
712 info->float_controls_mode = nir->info.float_controls_execution_mode;
713
714 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
715 /* If the i-th output is used, all previous outputs must be
716 * non-zero to match the target format.
717 * TODO: compact MRT to avoid holes and to remove this
718 * workaround.
719 */
720 unsigned num_targets = (util_last_bit(info->ps.cb_shader_mask) + 3) / 4;
721 for (unsigned i = 0; i < num_targets; i++) {
722 if (!(info->ps.cb_shader_mask & (0xfu << (i * 4)))) {
723 info->ps.cb_shader_mask |= 0xfu << (i * 4);
724 }
725 }
726
727 if (key->fs.is_dual_src) {
728 info->ps.cb_shader_mask |= (info->ps.cb_shader_mask & 0xf) << 4;
729 }
730 }
731 }
732