• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /* Copyright (C) 2007-2008 Jean-Marc Valin
2  * Copyright (C) 2008 Thorvald Natvig
3  * Copyright (C) 2011 Texas Instruments
4  *               author Jyri Sarha
5  */
6 /**
7    @file resample_neon.h
8    @brief Resampler functions (NEON version)
9 */
10 /*
11    Redistribution and use in source and binary forms, with or without
12    modification, are permitted provided that the following conditions
13    are met:
14 
15    - Redistributions of source code must retain the above copyright
16    notice, this list of conditions and the following disclaimer.
17 
18    - Redistributions in binary form must reproduce the above copyright
19    notice, this list of conditions and the following disclaimer in the
20    documentation and/or other materials provided with the distribution.
21 
22    - Neither the name of the Xiph.org Foundation nor the names of its
23    contributors may be used to endorse or promote products derived from
24    this software without specific prior written permission.
25 
26    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27    ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28    LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29    A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR
30    CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31    EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32    PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33    PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34    LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35    NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38 
39 #include <arm_neon.h>
40 
41 #ifdef FIXED_POINT
42 #ifdef __thumb2__
saturate_32bit_to_16bit(int32_t a)43 static inline int32_t saturate_32bit_to_16bit(int32_t a) {
44     int32_t ret;
45     asm ("ssat %[ret], #16, %[a]"
46          : [ret] "=&r" (ret)
47          : [a] "r" (a)
48          : );
49     return ret;
50 }
51 #else
saturate_32bit_to_16bit(int32_t a)52 static inline int32_t saturate_32bit_to_16bit(int32_t a) {
53     int32_t ret;
54     asm ("vmov.s32 d0[0], %[a]\n"
55          "vqmovn.s32 d0, q0\n"
56          "vmov.s16 %[ret], d0[0]\n"
57          : [ret] "=&r" (ret)
58          : [a] "r" (a)
59          : "q0");
60     return ret;
61 }
62 #endif
63 #undef WORD2INT
64 #define WORD2INT(x) (saturate_32bit_to_16bit(x))
65 
66 #define OVERRIDE_INNER_PRODUCT_SINGLE
67 /* Only works when len % 4 == 0 */
inner_product_single(const int16_t * a,const int16_t * b,unsigned int len)68 static inline int32_t inner_product_single(const int16_t *a, const int16_t *b, unsigned int len)
69 {
70     int32_t ret;
71     uint32_t remainder = len % 16;
72     len = len - remainder;
73 
74     asm volatile ("	 cmp %[len], #0\n"
75 		  "	 bne 1f\n"
76 		  "	 vld1.16 {d16}, [%[b]]!\n"
77 		  "	 vld1.16 {d20}, [%[a]]!\n"
78 		  "	 subs %[remainder], %[remainder], #4\n"
79 		  "	 vmull.s16 q0, d16, d20\n"
80 		  "      beq 5f\n"
81 		  "	 b 4f\n"
82 		  "1:"
83 		  "	 vld1.16 {d16, d17, d18, d19}, [%[b]]!\n"
84 		  "	 vld1.16 {d20, d21, d22, d23}, [%[a]]!\n"
85 		  "	 subs %[len], %[len], #16\n"
86 		  "	 vmull.s16 q0, d16, d20\n"
87 		  "	 vmlal.s16 q0, d17, d21\n"
88 		  "	 vmlal.s16 q0, d18, d22\n"
89 		  "	 vmlal.s16 q0, d19, d23\n"
90 		  "	 beq 3f\n"
91 		  "2:"
92 		  "	 vld1.16 {d16, d17, d18, d19}, [%[b]]!\n"
93 		  "	 vld1.16 {d20, d21, d22, d23}, [%[a]]!\n"
94 		  "	 subs %[len], %[len], #16\n"
95 		  "	 vmlal.s16 q0, d16, d20\n"
96 		  "	 vmlal.s16 q0, d17, d21\n"
97 		  "	 vmlal.s16 q0, d18, d22\n"
98 		  "	 vmlal.s16 q0, d19, d23\n"
99 		  "	 bne 2b\n"
100 		  "3:"
101 		  "	 cmp %[remainder], #0\n"
102 		  "	 beq 5f\n"
103 		  "4:"
104 		  "	 vld1.16 {d16}, [%[b]]!\n"
105 		  "	 vld1.16 {d20}, [%[a]]!\n"
106 		  "	 subs %[remainder], %[remainder], #4\n"
107 		  "	 vmlal.s16 q0, d16, d20\n"
108 		  "	 bne 4b\n"
109 		  "5:"
110 		  "	 vaddl.s32 q0, d0, d1\n"
111 		  "	 vadd.s64 d0, d0, d1\n"
112 		  "	 vqmovn.s64 d0, q0\n"
113 		  "	 vqrshrn.s32 d0, q0, #15\n"
114 		  "	 vmov.s16 %[ret], d0[0]\n"
115 		  : [ret] "=&r" (ret), [a] "+r" (a), [b] "+r" (b),
116 		    [len] "+r" (len), [remainder] "+r" (remainder)
117 		  :
118 		  : "cc", "q0",
119 		    "d16", "d17", "d18", "d19",
120 		    "d20", "d21", "d22", "d23");
121 
122     return ret;
123 }
124 #elif defined(FLOATING_POINT)
125 
saturate_float_to_16bit(float a)126 static inline int32_t saturate_float_to_16bit(float a) {
127     int32_t ret;
128     asm ("vmov.f32 d0[0], %[a]\n"
129          "vcvt.s32.f32 d0, d0, #15\n"
130          "vqrshrn.s32 d0, q0, #15\n"
131          "vmov.s16 %[ret], d0[0]\n"
132          : [ret] "=&r" (ret)
133          : [a] "r" (a)
134          : "q0");
135     return ret;
136 }
137 #undef WORD2INT
138 #define WORD2INT(x) (saturate_float_to_16bit(x))
139 
140 #define OVERRIDE_INNER_PRODUCT_SINGLE
141 /* Only works when len % 4 == 0 */
inner_product_single(const float * a,const float * b,unsigned int len)142 static inline float inner_product_single(const float *a, const float *b, unsigned int len)
143 {
144     float ret;
145     uint32_t remainder = len % 16;
146     len = len - remainder;
147 
148     asm volatile ("	 cmp %[len], #0\n"
149 		  "	 bne 1f\n"
150 		  "	 vld1.32 {q4}, [%[b]]!\n"
151 		  "	 vld1.32 {q8}, [%[a]]!\n"
152 		  "	 subs %[remainder], %[remainder], #4\n"
153 		  "	 vmul.f32 q0, q4, q8\n"
154 		  "      bne 4f\n"
155 		  "	 b 5f\n"
156 		  "1:"
157 		  "	 vld1.32 {q4, q5}, [%[b]]!\n"
158 		  "	 vld1.32 {q8, q9}, [%[a]]!\n"
159 		  "	 vld1.32 {q6, q7}, [%[b]]!\n"
160 		  "	 vld1.32 {q10, q11}, [%[a]]!\n"
161 		  "	 subs %[len], %[len], #16\n"
162 		  "	 vmul.f32 q0, q4, q8\n"
163 		  "	 vmul.f32 q1, q5, q9\n"
164 		  "	 vmul.f32 q2, q6, q10\n"
165 		  "	 vmul.f32 q3, q7, q11\n"
166 		  "	 beq 3f\n"
167 		  "2:"
168 		  "	 vld1.32 {q4, q5}, [%[b]]!\n"
169 		  "	 vld1.32 {q8, q9}, [%[a]]!\n"
170 		  "	 vld1.32 {q6, q7}, [%[b]]!\n"
171 		  "	 vld1.32 {q10, q11}, [%[a]]!\n"
172 		  "	 subs %[len], %[len], #16\n"
173 		  "	 vmla.f32 q0, q4, q8\n"
174 		  "	 vmla.f32 q1, q5, q9\n"
175 		  "	 vmla.f32 q2, q6, q10\n"
176 		  "	 vmla.f32 q3, q7, q11\n"
177 		  "	 bne 2b\n"
178 		  "3:"
179 		  "	 vadd.f32 q4, q0, q1\n"
180 		  "	 vadd.f32 q5, q2, q3\n"
181 		  "	 cmp %[remainder], #0\n"
182 		  "	 vadd.f32 q0, q4, q5\n"
183 		  "	 beq 5f\n"
184 		  "4:"
185 		  "	 vld1.32 {q6}, [%[b]]!\n"
186 		  "	 vld1.32 {q10}, [%[a]]!\n"
187 		  "	 subs %[remainder], %[remainder], #4\n"
188 		  "	 vmla.f32 q0, q6, q10\n"
189 		  "	 bne 4b\n"
190 		  "5:"
191 		  "	 vadd.f32 d0, d0, d1\n"
192 		  "	 vpadd.f32 d0, d0, d0\n"
193 		  "	 vmov.f32 %[ret], d0[0]\n"
194 		  : [ret] "=&r" (ret), [a] "+r" (a), [b] "+r" (b),
195 		    [len] "+l" (len), [remainder] "+l" (remainder)
196 		  :
197 		  : "cc", "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8",
198                     "q9", "q10", "q11");
199     return ret;
200 }
201 #endif
202