1 /*
2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <drivers/arm/ccn.h>
14 #include <plat/arm/common/plat_arm.h>
15 #include <plat/common/platform.h>
16 #include <drivers/arm/sbsa.h>
17 #include <sgi_base_platform_def.h>
18
19 #if SPM_MM
20 #include <services/spm_mm_partition.h>
21 #endif
22
23 #define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
24 V2M_FLASH0_SIZE, \
25 MT_DEVICE | MT_RO | MT_SECURE)
26 /*
27 * Table of regions for different BL stages to map using the MMU.
28 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
29 * arm_configure_mmu_elx() will give the available subset of that.
30 *
31 * Replace or extend the below regions as required
32 */
33 #if IMAGE_BL1
34 const mmap_region_t plat_arm_mmap[] = {
35 ARM_MAP_SHARED_RAM,
36 SGI_MAP_FLASH0_RO,
37 CSS_SGI_MAP_DEVICE,
38 SOC_CSS_MAP_DEVICE,
39 {0}
40 };
41 #endif
42 #if IMAGE_BL2
43 const mmap_region_t plat_arm_mmap[] = {
44 ARM_MAP_SHARED_RAM,
45 SGI_MAP_FLASH0_RO,
46 #ifdef PLAT_ARM_MEM_PROT_ADDR
47 ARM_V2M_MAP_MEM_PROTECT,
48 #endif
49 CSS_SGI_MAP_DEVICE,
50 SOC_CSS_MAP_DEVICE,
51 ARM_MAP_NS_DRAM1,
52 #if ARM_BL31_IN_DRAM
53 ARM_MAP_BL31_SEC_DRAM,
54 #endif
55 #if SPM_MM
56 ARM_SP_IMAGE_MMAP,
57 #endif
58 #if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
59 ARM_MAP_BL1_RW,
60 #endif
61 {0}
62 };
63 #endif
64 #if IMAGE_BL31
65 const mmap_region_t plat_arm_mmap[] = {
66 ARM_MAP_SHARED_RAM,
67 V2M_MAP_IOFPGA,
68 CSS_SGI_MAP_DEVICE,
69 #ifdef PLAT_ARM_MEM_PROT_ADDR
70 ARM_V2M_MAP_MEM_PROTECT,
71 #endif
72 SOC_CSS_MAP_DEVICE,
73 #if SPM_MM
74 ARM_SPM_BUF_EL3_MMAP,
75 #endif
76 {0}
77 };
78
79 #if SPM_MM && defined(IMAGE_BL31)
80 const mmap_region_t plat_arm_secure_partition_mmap[] = {
81 PLAT_ARM_SECURE_MAP_DEVICE,
82 ARM_SP_IMAGE_MMAP,
83 ARM_SP_IMAGE_NS_BUF_MMAP,
84 ARM_SP_CPER_BUF_MMAP,
85 ARM_SP_IMAGE_RW_MMAP,
86 ARM_SPM_BUF_EL0_MMAP,
87 {0}
88 };
89 #endif /* SPM_MM && defined(IMAGE_BL31) */
90 #endif
91
92 ARM_CASSERT_MMAP
93
94 #if SPM_MM && defined(IMAGE_BL31)
95 /*
96 * Boot information passed to a secure partition during initialisation. Linear
97 * indices in MP information will be filled at runtime.
98 */
99 static spm_mm_mp_info_t sp_mp_info[] = {
100 [0] = {0x81000000, 0},
101 [1] = {0x81000100, 0},
102 [2] = {0x81000200, 0},
103 [3] = {0x81000300, 0},
104 [4] = {0x81010000, 0},
105 [5] = {0x81010100, 0},
106 [6] = {0x81010200, 0},
107 [7] = {0x81010300, 0},
108 };
109
110 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
111 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
112 .h.version = VERSION_1,
113 .h.size = sizeof(spm_mm_boot_info_t),
114 .h.attr = 0,
115 .sp_mem_base = ARM_SP_IMAGE_BASE,
116 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
117 .sp_image_base = ARM_SP_IMAGE_BASE,
118 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
119 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
120 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
121 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
122 .sp_image_size = ARM_SP_IMAGE_SIZE,
123 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
124 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
125 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
126 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
127 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
128 .num_cpus = PLATFORM_CORE_COUNT,
129 .mp_info = &sp_mp_info[0],
130 };
131
plat_get_secure_partition_mmap(void * cookie)132 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
133 {
134 return plat_arm_secure_partition_mmap;
135 }
136
plat_get_secure_partition_boot_info(void * cookie)137 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
138 void *cookie)
139 {
140 return &plat_arm_secure_partition_boot_info;
141 }
142 #endif /* SPM_MM && defined(IMAGE_BL31) */
143
144 #if TRUSTED_BOARD_BOOT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)145 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
146 {
147 assert(heap_addr != NULL);
148 assert(heap_size != NULL);
149
150 return arm_get_mbedtls_heap(heap_addr, heap_size);
151 }
152 #endif
153
plat_arm_secure_wdt_start(void)154 void plat_arm_secure_wdt_start(void)
155 {
156 sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
157 }
158
plat_arm_secure_wdt_stop(void)159 void plat_arm_secure_wdt_stop(void)
160 {
161 sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
162 }
163