1/* Copyright (C) 2005 Psi Systems, Inc. 2 File: speex_C54_test.cmd 3 Linker command file with memory allocation for TI TMS320VC5416 processor 4 for use with TI Code Composer (TM) DSP development tools. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions 8 are met: 9 10 - Redistributions of source code must retain the above copyright 11 notice, this list of conditions and the following disclaimer. 12 13 - Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 - Neither the name of the Xiph.org Foundation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR 25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 26 EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 28 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 29 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32*/ 33 34-c 35-stack 0x2000 36-heap 0x1000 /* If private memory allocation is used for Speex */ 37/*-heap 0x6000 /* If calloc is used for Speex */ 38-lrts_ext.lib 39 40MEMORY 41{ 42/* PAGE 0: P_DARAM03: origin = 0x80, len = 0x7f00*/ 43 PAGE 0: P_DARAM03: origin = 0x5000, len = 0x2f80 44 PAGE 0: VECT: origin = 0x7f80, len = 0x80 45 PAGE 0: P_DARAM47: origin = 0x18000, len = 0x8000 46 PAGE 0: SARAM03: origin = 0x28000, len = 0x8000 47 PAGE 0: SARAM47: origin = 0x38000, len = 0x8000 48 49 PAGE 1: USERREGS: origin = 0x60, len = 0x1a 50 PAGE 1: BIOSREGS: origin = 0x7c, len = 0x4 51 PAGE 1: CSLREGS: origin = 0x7a, len = 0x2 52 D_DARAM03: origin = 0x80, len = 0x4f80 53 D_DARAM47: origin = 0x8000, len = 0x8000 54} 55 56SECTIONS 57{ 58 .vectors: {} > VECT PAGE 0 59 .bootmem: {rts_ext.lib (.text)} > P_DARAM03 PAGE 0 60/* .bootmem: {} > P_DARAM03 PAGE 0 */ 61 .text: {} > SARAM03 PAGE 0 62 .cinit: {} > SARAM03 PAGE 0 63 .switch: {} > SARAM03 PAGE 0 64 .bss: {} > D_DARAM03 | D_DARAM47 PAGE 1 65 .far: {} > D_DARAM03 | D_DARAM47 PAGE 1 66 .const: {} > D_DARAM03 | D_DARAM47 PAGE 1 67 .sysmem: {} > D_DARAM47 PAGE 1 68 .cio: {} > D_DARAM03 | D_DARAM47 PAGE 1 69 .stack: {} > D_DARAM03 | D_DARAM47 PAGE 1 70 .myheap: {} > D_DARAM47 PAGE 1 71} 72