1/* 2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <context.h> 11 12/* ----------------------------------------------------------------------------- 13 * Very simple stackless exception handlers used by the spm shim layer. 14 * ----------------------------------------------------------------------------- 15 */ 16 .globl spm_shim_exceptions_ptr 17 18vector_base spm_shim_exceptions_ptr, .spm_shim_exceptions 19 20 /* ----------------------------------------------------- 21 * Current EL with SP0 : 0x0 - 0x200 22 * ----------------------------------------------------- 23 */ 24vector_entry SynchronousExceptionSP0, .spm_shim_exceptions 25 b . 26end_vector_entry SynchronousExceptionSP0 27 28vector_entry IrqSP0, .spm_shim_exceptions 29 b . 30end_vector_entry IrqSP0 31 32vector_entry FiqSP0, .spm_shim_exceptions 33 b . 34end_vector_entry FiqSP0 35 36vector_entry SErrorSP0, .spm_shim_exceptions 37 b . 38end_vector_entry SErrorSP0 39 40 /* ----------------------------------------------------- 41 * Current EL with SPx: 0x200 - 0x400 42 * ----------------------------------------------------- 43 */ 44vector_entry SynchronousExceptionSPx, .spm_shim_exceptions 45 b . 46end_vector_entry SynchronousExceptionSPx 47 48vector_entry IrqSPx, .spm_shim_exceptions 49 b . 50end_vector_entry IrqSPx 51 52vector_entry FiqSPx, .spm_shim_exceptions 53 b . 54end_vector_entry FiqSPx 55 56vector_entry SErrorSPx, .spm_shim_exceptions 57 b . 58end_vector_entry SErrorSPx 59 60 /* ----------------------------------------------------- 61 * Lower EL using AArch64 : 0x400 - 0x600. No exceptions 62 * are handled since secure_partition does not implement 63 * a lower EL 64 * ----------------------------------------------------- 65 */ 66vector_entry SynchronousExceptionA64, .spm_shim_exceptions 67 msr tpidr_el1, x30 68 mrs x30, esr_el1 69 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 70 71 cmp x30, #EC_AARCH64_SVC 72 b.eq do_smc 73 74 cmp x30, #EC_AARCH32_SVC 75 b.eq do_smc 76 77 cmp x30, #EC_AARCH64_SYS 78 b.eq handle_sys_trap 79 80 /* Fail in all the other cases */ 81 b panic 82 83 /* --------------------------------------------- 84 * Tell SPM that we are done initialising 85 * --------------------------------------------- 86 */ 87do_smc: 88 mrs x30, tpidr_el1 89 smc #0 90 exception_return 91 92 /* AArch64 system instructions trap are handled as a panic for now */ 93handle_sys_trap: 94panic: 95 b panic 96end_vector_entry SynchronousExceptionA64 97 98vector_entry IrqA64, .spm_shim_exceptions 99 b . 100end_vector_entry IrqA64 101 102vector_entry FiqA64, .spm_shim_exceptions 103 b . 104end_vector_entry FiqA64 105 106vector_entry SErrorA64, .spm_shim_exceptions 107 b . 108end_vector_entry SErrorA64 109 110 /* ----------------------------------------------------- 111 * Lower EL using AArch32 : 0x600 - 0x800 112 * ----------------------------------------------------- 113 */ 114vector_entry SynchronousExceptionA32, .spm_shim_exceptions 115 b . 116end_vector_entry SynchronousExceptionA32 117 118vector_entry IrqA32, .spm_shim_exceptions 119 b . 120end_vector_entry IrqA32 121 122vector_entry FiqA32, .spm_shim_exceptions 123 b . 124end_vector_entry FiqA32 125 126vector_entry SErrorA32, .spm_shim_exceptions 127 b . 128end_vector_entry SErrorA32 129