1// Copyright 2019 The Marl Authors. 2// 3// Licensed under the Apache License, Version 2.0 (the "License"); 4// you may not use this file except in compliance with the License. 5// You may obtain a copy of the License at 6// 7// https://www.apache.org/licenses/LICENSE-2.0 8// 9// Unless required by applicable law or agreed to in writing, software 10// distributed under the License is distributed on an "AS IS" BASIS, 11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12// See the License for the specific language governing permissions and 13// limitations under the License. 14 15#if defined(__arm__) 16 17#define MARL_BUILD_ASM 1 18#include "osfiber_asm_arm.h" 19 20// void marl_fiber_swap(marl_fiber_context* from, const marl_fiber_context* to) 21// x0: from 22// x1: to 23.text 24.global marl_fiber_swap 25.align 4 26.type marl_fiber_swap, %function 27marl_fiber_swap: 28 29 // Save context 'from' 30 // TODO: multiple registers can be stored in a single instruction with: stm rA, {rB-rC} 31 32 // Store special purpose registers 33 str r12, [r0, #MARL_REG_r12] 34 35 // Store callee-preserved registers 36 str r4, [r0, #MARL_REG_r4] 37 str r5, [r0, #MARL_REG_r5] 38 str r6, [r0, #MARL_REG_r6] 39 str r7, [r0, #MARL_REG_r7] 40 str r8, [r0, #MARL_REG_r8] 41 str r9, [r0, #MARL_REG_r9] 42 str r10, [r0, #MARL_REG_r10] 43 str r11, [r0, #MARL_REG_r11] 44 45 // Store sp, lr and pc 46 str sp, [r0, #MARL_REG_SP] 47 str lr, [r0, #MARL_REG_LR] 48 49 // Load context 'to' 50 // TODO: multiple registers can be loaded in a single instruction with: ldm rA, {rB-rC} 51 mov r3, r1 52 53 // Load special purpose registers 54 ldr r12, [r3, #MARL_REG_r12] 55 56 // Load callee-preserved registers 57 ldr r4, [r3, #MARL_REG_r4] 58 ldr r5, [r3, #MARL_REG_r5] 59 ldr r6, [r3, #MARL_REG_r6] 60 ldr r7, [r3, #MARL_REG_r7] 61 ldr r8, [r3, #MARL_REG_r8] 62 ldr r9, [r3, #MARL_REG_r9] 63 ldr r10, [r3, #MARL_REG_r10] 64 ldr r11, [r3, #MARL_REG_r11] 65 66 // Load parameter registers 67 ldr r0, [r3, #MARL_REG_r0] 68 ldr r1, [r3, #MARL_REG_r1] 69 70 // Load sp, lr and pc 71 ldr sp, [r3, #MARL_REG_SP] 72 ldr lr, [r3, #MARL_REG_LR] 73 mov pc, lr 74 75#endif // defined(__arm__) 76