1 /* Capstone Disassembler Engine */
2 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013 */
3
4 #include <stdio.h>
5 #include <stdlib.h>
6
7 #include <capstone/platform.h>
8 #include <capstone/capstone.h>
9
10 struct platform {
11 cs_arch arch;
12 cs_mode mode;
13 unsigned char *code;
14 size_t size;
15 const char *comment;
16 cs_opt_type opt_type;
17 cs_opt_value opt_value;
18 };
19
print_string_hex(unsigned char * str,size_t len)20 static void print_string_hex(unsigned char *str, size_t len)
21 {
22 unsigned char *c;
23
24 printf("Code: ");
25 for (c = str; c < str + len; c++) {
26 printf("0x%02x ", *c & 0xff);
27 }
28 printf("\n");
29 }
30
test()31 static void test()
32 {
33 #ifdef CAPSTONE_HAS_X86
34 #define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
35 #define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
36 //#define X86_CODE32 "\x0f\xa7\xc0" // xstorerng
37 #define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
38 #endif
39 #ifdef CAPSTONE_HAS_ARM
40 //#define ARM_CODE "\x04\xe0\x2d\xe5"
41 #define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
42 #define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
43 #define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
44 #define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
45 #define THUMB_MCLASS "\xef\xf3\x02\x80"
46 #define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
47 #endif
48 #ifdef CAPSTONE_HAS_MIPS
49 #define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08"
50 //#define MIPS_CODE "\x21\x38\x00\x01"
51 //#define MIPS_CODE "\x21\x30\xe6\x70"
52 //#define MIPS_CODE "\x1c\x00\x40\x14"
53 #define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
54 #define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
55 #define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0"
56 #endif
57 #ifdef CAPSTONE_HAS_ARM64
58 //#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8]
59 //#define ARM64_CODE "\x00\x40\x21\x4b" // sub w0, w0, w1, uxtw
60 //#define ARM64_CODE "\x21\x7c\x02\x9b" // mul x1, x1, x2
61 //#define ARM64_CODE "\x20\x74\x0b\xd5" // dc zva, x0
62 //#define ARM64_CODE "\x20\xfc\x02\x9b" // mneg x0, x1, x2
63 //#define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x10\x20\x21\x1e"
64 //#define ARM64_CODE "\x21\x7c\x00\x53"
65 #define ARM64_CODE "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
66 #endif
67 //#define THUMB_CODE "\x0a\xbf" // itet eq
68 //#define X86_CODE32 "\x77\x04" // ja +6
69 #ifdef CAPSTONE_HAS_POWERPC
70 #define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
71 #define PPC_CODE2 "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
72 #endif
73 #ifdef CAPSTONE_HAS_SPARC
74 #define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
75 #define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
76 #endif
77 #ifdef CAPSTONE_HAS_SYSZ
78 #define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
79 #endif
80 #ifdef CAPSTONE_HAS_XCORE
81 #define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
82 #endif
83 #ifdef CAPSTONE_HAS_M68K
84 #define M68K_CODE "\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28"
85 #endif
86 #ifdef CAPSTONE_HAS_M680X
87 #define M680X_CODE "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
88 #endif
89 #ifdef CAPSTONE_HAS_MOS65XX
90 #define MOS65XX_CODE "\x0A\x00\xFE\x34\x12\xD0\xFF\xEA\x19\x56\x34\x46\x80"
91 #endif
92
93
94 struct platform platforms[] = {
95 #ifdef CAPSTONE_HAS_X86
96 {
97 CS_ARCH_X86,
98 CS_MODE_16,
99 (unsigned char *)X86_CODE16,
100 sizeof(X86_CODE32) - 1,
101 "X86 16bit (Intel syntax)"
102 },
103 {
104 CS_ARCH_X86,
105 CS_MODE_32,
106 (unsigned char *)X86_CODE32,
107 sizeof(X86_CODE32) - 1,
108 "X86 32bit (ATT syntax)",
109 CS_OPT_SYNTAX,
110 CS_OPT_SYNTAX_ATT,
111 },
112 {
113 CS_ARCH_X86,
114 CS_MODE_32,
115 (unsigned char *)X86_CODE32,
116 sizeof(X86_CODE32) - 1,
117 "X86 32 (Intel syntax)"
118 },
119 {
120 CS_ARCH_X86,
121 CS_MODE_64,
122 (unsigned char *)X86_CODE64,
123 sizeof(X86_CODE64) - 1,
124 "X86 64 (Intel syntax)"
125 },
126 #endif
127 #ifdef CAPSTONE_HAS_ARM
128 {
129 CS_ARCH_ARM,
130 CS_MODE_ARM,
131 (unsigned char *)ARM_CODE,
132 sizeof(ARM_CODE) - 1,
133 "ARM"
134 },
135 {
136 CS_ARCH_ARM,
137 CS_MODE_THUMB,
138 (unsigned char *)THUMB_CODE2,
139 sizeof(THUMB_CODE2) - 1,
140 "THUMB-2"
141 },
142 {
143 CS_ARCH_ARM,
144 CS_MODE_ARM,
145 (unsigned char *)ARM_CODE2,
146 sizeof(ARM_CODE2) - 1,
147 "ARM: Cortex-A15 + NEON"
148 },
149 {
150 CS_ARCH_ARM,
151 CS_MODE_THUMB,
152 (unsigned char *)THUMB_CODE,
153 sizeof(THUMB_CODE) - 1,
154 "THUMB"
155 },
156 {
157 CS_ARCH_ARM,
158 (cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS),
159 (unsigned char*)THUMB_MCLASS,
160 sizeof(THUMB_MCLASS) - 1,
161 "Thumb-MClass"
162 },
163 {
164 CS_ARCH_ARM,
165 (cs_mode)(CS_MODE_ARM + CS_MODE_V8),
166 (unsigned char*)ARMV8,
167 sizeof(ARMV8) - 1,
168 "Arm-V8"
169 },
170 #endif
171 #ifdef CAPSTONE_HAS_MIPS
172 {
173 CS_ARCH_MIPS,
174 (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
175 (unsigned char *)MIPS_CODE,
176 sizeof(MIPS_CODE) - 1,
177 "MIPS-32 (Big-endian)"
178 },
179 {
180 CS_ARCH_MIPS,
181 (cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN),
182 (unsigned char *)MIPS_CODE2,
183 sizeof(MIPS_CODE2) - 1,
184 "MIPS-64-EL (Little-endian)"
185 },
186 {
187 CS_ARCH_MIPS,
188 (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
189 (unsigned char*)MIPS_32R6M,
190 sizeof(MIPS_32R6M) - 1,
191 "MIPS-32R6 | Micro (Big-endian)"
192 },
193 {
194 CS_ARCH_MIPS,
195 (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
196 (unsigned char*)MIPS_32R6,
197 sizeof(MIPS_32R6) - 1,
198 "MIPS-32R6 (Big-endian)"
199 },
200 #endif
201 #ifdef CAPSTONE_HAS_ARM64
202 {
203 CS_ARCH_ARM64,
204 CS_MODE_ARM,
205 (unsigned char *)ARM64_CODE,
206 sizeof(ARM64_CODE) - 1,
207 "ARM-64"
208 },
209 #endif
210 #ifdef CAPSTONE_HAS_POWERPC
211 {
212 CS_ARCH_PPC,
213 CS_MODE_BIG_ENDIAN,
214 (unsigned char*)PPC_CODE,
215 sizeof(PPC_CODE) - 1,
216 "PPC-64"
217 },
218 {
219 CS_ARCH_PPC,
220 CS_MODE_BIG_ENDIAN + CS_MODE_QPX,
221 (unsigned char*)PPC_CODE2,
222 sizeof(PPC_CODE2) - 1,
223 "PPC-64 + QPX",
224 },
225 #endif
226 #ifdef CAPSTONE_HAS_SPARC
227 {
228 CS_ARCH_SPARC,
229 CS_MODE_BIG_ENDIAN,
230 (unsigned char*)SPARC_CODE,
231 sizeof(SPARC_CODE) - 1,
232 "Sparc"
233 },
234 {
235 CS_ARCH_SPARC,
236 (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9),
237 (unsigned char*)SPARCV9_CODE,
238 sizeof(SPARCV9_CODE) - 1,
239 "SparcV9"
240 },
241 #endif
242 #ifdef CAPSTONE_HAS_SYSZ
243 {
244 CS_ARCH_SYSZ,
245 (cs_mode)0,
246 (unsigned char*)SYSZ_CODE,
247 sizeof(SYSZ_CODE) - 1,
248 "SystemZ"
249 },
250 #endif
251 #ifdef CAPSTONE_HAS_XCORE
252 {
253 CS_ARCH_XCORE,
254 (cs_mode)0,
255 (unsigned char*)XCORE_CODE,
256 sizeof(XCORE_CODE) - 1,
257 "XCore"
258 },
259 #endif
260 #ifdef CAPSTONE_HAS_M68K
261 {
262 CS_ARCH_M68K,
263 (cs_mode)(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040),
264 (unsigned char*)M68K_CODE,
265 sizeof(M68K_CODE) - 1,
266 "M68K",
267 },
268 #endif
269 #ifdef CAPSTONE_HAS_M680X
270 {
271 CS_ARCH_M680X,
272 (cs_mode)(CS_MODE_M680X_6809),
273 (unsigned char*)M680X_CODE,
274 sizeof(M680X_CODE) - 1,
275 "M680X_M6809",
276 },
277 #endif
278 #ifdef CAPSTONE_HAS_MOS65XX
279 {
280 CS_ARCH_MOS65XX,
281 (cs_mode)0,
282 (unsigned char*)MOS65XX_CODE,
283 sizeof(MOS65XX_CODE) - 1,
284 "MOS65XX",
285 },
286 #endif
287 };
288
289 csh handle;
290 uint64_t address = 0x1000;
291 cs_insn *all_insn;
292 cs_detail *detail;
293 int i;
294 size_t count;
295 cs_err err;
296
297 for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
298 printf("****************\n");
299 printf("Platform: %s\n", platforms[i].comment);
300 err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
301 if (err) {
302 printf("Failed on cs_open() with error returned: %u\n", err);
303 abort();
304 }
305
306 if (platforms[i].opt_type)
307 cs_option(handle, platforms[i].opt_type, platforms[i].opt_value);
308
309 cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
310
311 count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &all_insn);
312 if (count) {
313 size_t j;
314 int n;
315
316 print_string_hex(platforms[i].code, platforms[i].size);
317 printf("Disasm:\n");
318
319 for (j = 0; j < count; j++) {
320 cs_insn *in = &(all_insn[j]);
321 printf("0x%" PRIx64 ":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n",
322 in->address, in->mnemonic, in->op_str,
323 in->id, cs_insn_name(handle, in->id));
324
325 // print implicit registers used by this instruction
326 detail = in->detail;
327
328 if (detail->regs_read_count > 0) {
329 printf("\tImplicit registers read: ");
330 for (n = 0; n < detail->regs_read_count; n++) {
331 printf("%s ", cs_reg_name(handle, detail->regs_read[n]));
332 }
333 printf("\n");
334 }
335
336 // print implicit registers modified by this instruction
337 if (detail->regs_write_count > 0) {
338 printf("\tImplicit registers modified: ");
339 for (n = 0; n < detail->regs_write_count; n++) {
340 printf("%s ", cs_reg_name(handle, detail->regs_write[n]));
341 }
342 printf("\n");
343 }
344
345 // print the groups this instruction belong to
346 if (detail->groups_count > 0) {
347 printf("\tThis instruction belongs to groups: ");
348 for (n = 0; n < detail->groups_count; n++) {
349 printf("%s ", cs_group_name(handle, detail->groups[n]));
350 }
351 printf("\n");
352 }
353 }
354
355 // print out the next offset, after the last insn
356 printf("0x%" PRIx64 ":\n", all_insn[j-1].address + all_insn[j-1].size);
357
358 // free memory allocated by cs_disasm()
359 cs_free(all_insn, count);
360 } else {
361 printf("****************\n");
362 printf("Platform: %s\n", platforms[i].comment);
363 print_string_hex(platforms[i].code, platforms[i].size);
364 printf("ERROR: Failed to disasm given code!\n");
365 abort();
366 }
367
368 printf("\n");
369
370 cs_close(&handle);
371 }
372 }
373
main()374 int main()
375 {
376 test();
377
378 return 0;
379 }
380