1 /* Capstone Disassembler Engine */
2 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013 */
3
4 #include <stdio.h>
5 #include <stdlib.h>
6
7 #include <capstone/platform.h>
8 #include <capstone/capstone.h>
9
10 static csh handle;
11
12 struct platform {
13 cs_arch arch;
14 cs_mode mode;
15 unsigned char *code;
16 size_t size;
17 const char *comment;
18 cs_opt_type opt_type;
19 cs_opt_value opt_value;
20 };
21
print_string_hex(const char * comment,unsigned char * str,size_t len)22 static void print_string_hex(const char *comment, unsigned char *str, size_t len)
23 {
24 unsigned char *c;
25
26 printf("%s", comment);
27 for (c = str; c < str + len; c++) {
28 printf("0x%02x ", *c & 0xff);
29 }
30
31 printf("\n");
32 }
33
get_eflag_name(uint64_t flag)34 static const char *get_eflag_name(uint64_t flag)
35 {
36 switch(flag) {
37 default:
38 return NULL;
39 case X86_EFLAGS_UNDEFINED_OF:
40 return "UNDEF_OF";
41 case X86_EFLAGS_UNDEFINED_SF:
42 return "UNDEF_SF";
43 case X86_EFLAGS_UNDEFINED_ZF:
44 return "UNDEF_ZF";
45 case X86_EFLAGS_MODIFY_AF:
46 return "MOD_AF";
47 case X86_EFLAGS_UNDEFINED_PF:
48 return "UNDEF_PF";
49 case X86_EFLAGS_MODIFY_CF:
50 return "MOD_CF";
51 case X86_EFLAGS_MODIFY_SF:
52 return "MOD_SF";
53 case X86_EFLAGS_MODIFY_ZF:
54 return "MOD_ZF";
55 case X86_EFLAGS_UNDEFINED_AF:
56 return "UNDEF_AF";
57 case X86_EFLAGS_MODIFY_PF:
58 return "MOD_PF";
59 case X86_EFLAGS_UNDEFINED_CF:
60 return "UNDEF_CF";
61 case X86_EFLAGS_MODIFY_OF:
62 return "MOD_OF";
63 case X86_EFLAGS_RESET_OF:
64 return "RESET_OF";
65 case X86_EFLAGS_RESET_CF:
66 return "RESET_CF";
67 case X86_EFLAGS_RESET_DF:
68 return "RESET_DF";
69 case X86_EFLAGS_RESET_IF:
70 return "RESET_IF";
71 case X86_EFLAGS_TEST_OF:
72 return "TEST_OF";
73 case X86_EFLAGS_TEST_SF:
74 return "TEST_SF";
75 case X86_EFLAGS_TEST_ZF:
76 return "TEST_ZF";
77 case X86_EFLAGS_TEST_PF:
78 return "TEST_PF";
79 case X86_EFLAGS_TEST_CF:
80 return "TEST_CF";
81 case X86_EFLAGS_RESET_SF:
82 return "RESET_SF";
83 case X86_EFLAGS_RESET_AF:
84 return "RESET_AF";
85 case X86_EFLAGS_RESET_TF:
86 return "RESET_TF";
87 case X86_EFLAGS_RESET_NT:
88 return "RESET_NT";
89 case X86_EFLAGS_PRIOR_OF:
90 return "PRIOR_OF";
91 case X86_EFLAGS_PRIOR_SF:
92 return "PRIOR_SF";
93 case X86_EFLAGS_PRIOR_ZF:
94 return "PRIOR_ZF";
95 case X86_EFLAGS_PRIOR_AF:
96 return "PRIOR_AF";
97 case X86_EFLAGS_PRIOR_PF:
98 return "PRIOR_PF";
99 case X86_EFLAGS_PRIOR_CF:
100 return "PRIOR_CF";
101 case X86_EFLAGS_PRIOR_TF:
102 return "PRIOR_TF";
103 case X86_EFLAGS_PRIOR_IF:
104 return "PRIOR_IF";
105 case X86_EFLAGS_PRIOR_DF:
106 return "PRIOR_DF";
107 case X86_EFLAGS_TEST_NT:
108 return "TEST_NT";
109 case X86_EFLAGS_TEST_DF:
110 return "TEST_DF";
111 case X86_EFLAGS_RESET_PF:
112 return "RESET_PF";
113 case X86_EFLAGS_PRIOR_NT:
114 return "PRIOR_NT";
115 case X86_EFLAGS_MODIFY_TF:
116 return "MOD_TF";
117 case X86_EFLAGS_MODIFY_IF:
118 return "MOD_IF";
119 case X86_EFLAGS_MODIFY_DF:
120 return "MOD_DF";
121 case X86_EFLAGS_MODIFY_NT:
122 return "MOD_NT";
123 case X86_EFLAGS_MODIFY_RF:
124 return "MOD_RF";
125 case X86_EFLAGS_SET_CF:
126 return "SET_CF";
127 case X86_EFLAGS_SET_DF:
128 return "SET_DF";
129 case X86_EFLAGS_SET_IF:
130 return "SET_IF";
131 }
132 }
133
get_fpu_flag_name(uint64_t flag)134 static const char *get_fpu_flag_name(uint64_t flag)
135 {
136 switch (flag) {
137 default:
138 return NULL;
139 case X86_FPU_FLAGS_MODIFY_C0:
140 return "MOD_C0";
141 case X86_FPU_FLAGS_MODIFY_C1:
142 return "MOD_C1";
143 case X86_FPU_FLAGS_MODIFY_C2:
144 return "MOD_C2";
145 case X86_FPU_FLAGS_MODIFY_C3:
146 return "MOD_C3";
147 case X86_FPU_FLAGS_RESET_C0:
148 return "RESET_C0";
149 case X86_FPU_FLAGS_RESET_C1:
150 return "RESET_C1";
151 case X86_FPU_FLAGS_RESET_C2:
152 return "RESET_C2";
153 case X86_FPU_FLAGS_RESET_C3:
154 return "RESET_C3";
155 case X86_FPU_FLAGS_SET_C0:
156 return "SET_C0";
157 case X86_FPU_FLAGS_SET_C1:
158 return "SET_C1";
159 case X86_FPU_FLAGS_SET_C2:
160 return "SET_C2";
161 case X86_FPU_FLAGS_SET_C3:
162 return "SET_C3";
163 case X86_FPU_FLAGS_UNDEFINED_C0:
164 return "UNDEF_C0";
165 case X86_FPU_FLAGS_UNDEFINED_C1:
166 return "UNDEF_C1";
167 case X86_FPU_FLAGS_UNDEFINED_C2:
168 return "UNDEF_C2";
169 case X86_FPU_FLAGS_UNDEFINED_C3:
170 return "UNDEF_C3";
171 case X86_FPU_FLAGS_TEST_C0:
172 return "TEST_C0";
173 case X86_FPU_FLAGS_TEST_C1:
174 return "TEST_C1";
175 case X86_FPU_FLAGS_TEST_C2:
176 return "TEST_C2";
177 case X86_FPU_FLAGS_TEST_C3:
178 return "TEST_C3";
179 }
180 }
181
print_insn_detail(csh ud,cs_mode mode,cs_insn * ins)182 static void print_insn_detail(csh ud, cs_mode mode, cs_insn *ins)
183 {
184 int count, i;
185 cs_x86 *x86;
186 cs_regs regs_read, regs_write;
187 uint8_t regs_read_count, regs_write_count;
188
189 // detail can be NULL on "data" instruction if SKIPDATA option is turned ON
190 if (ins->detail == NULL)
191 return;
192
193 x86 = &(ins->detail->x86);
194
195 print_string_hex("\tPrefix:", x86->prefix, 4);
196
197 print_string_hex("\tOpcode:", x86->opcode, 4);
198
199 printf("\trex: 0x%x\n", x86->rex);
200
201 printf("\taddr_size: %u\n", x86->addr_size);
202 printf("\tmodrm: 0x%x\n", x86->modrm);
203 if (x86->encoding.modrm_offset != 0) {
204 printf("\tmodrm_offset: 0x%x\n", x86->encoding.modrm_offset);
205 }
206
207 printf("\tdisp: 0x%" PRIx64 "\n", x86->disp);
208 if (x86->encoding.disp_offset != 0) {
209 printf("\tdisp_offset: 0x%x\n", x86->encoding.disp_offset);
210 }
211
212 if (x86->encoding.disp_size != 0) {
213 printf("\tdisp_size: 0x%x\n", x86->encoding.disp_size);
214 }
215
216 // SIB is not available in 16-bit mode
217 if ((mode & CS_MODE_16) == 0) {
218 printf("\tsib: 0x%x\n", x86->sib);
219 if (x86->sib_base != X86_REG_INVALID)
220 printf("\t\tsib_base: %s\n", cs_reg_name(handle, x86->sib_base));
221 if (x86->sib_index != X86_REG_INVALID)
222 printf("\t\tsib_index: %s\n", cs_reg_name(handle, x86->sib_index));
223 if (x86->sib_scale != 0)
224 printf("\t\tsib_scale: %d\n", x86->sib_scale);
225 }
226
227 // XOP code condition
228 if (x86->xop_cc != X86_XOP_CC_INVALID) {
229 printf("\txop_cc: %u\n", x86->xop_cc);
230 }
231
232 // SSE code condition
233 if (x86->sse_cc != X86_SSE_CC_INVALID) {
234 printf("\tsse_cc: %u\n", x86->sse_cc);
235 }
236
237 // AVX code condition
238 if (x86->avx_cc != X86_AVX_CC_INVALID) {
239 printf("\tavx_cc: %u\n", x86->avx_cc);
240 }
241
242 // AVX Suppress All Exception
243 if (x86->avx_sae) {
244 printf("\tavx_sae: %u\n", x86->avx_sae);
245 }
246
247 // AVX Rounding Mode
248 if (x86->avx_rm != X86_AVX_RM_INVALID) {
249 printf("\tavx_rm: %u\n", x86->avx_rm);
250 }
251
252 // Print out all immediate operands
253 count = cs_op_count(ud, ins, X86_OP_IMM);
254 if (count) {
255 printf("\timm_count: %u\n", count);
256 for (i = 1; i < count + 1; i++) {
257 int index = cs_op_index(ud, ins, X86_OP_IMM, i);
258 printf("\t\timms[%u]: 0x%" PRIx64 "\n", i, x86->operands[index].imm);
259 if (x86->encoding.imm_offset != 0) {
260 printf("\timm_offset: 0x%x\n", x86->encoding.imm_offset);
261 }
262
263 if (x86->encoding.imm_size != 0) {
264 printf("\timm_size: 0x%x\n", x86->encoding.imm_size);
265 }
266 }
267 }
268
269 if (x86->op_count)
270 printf("\top_count: %u\n", x86->op_count);
271
272 // Print out all operands
273 for (i = 0; i < x86->op_count; i++) {
274 cs_x86_op *op = &(x86->operands[i]);
275
276 switch((int)op->type) {
277 case X86_OP_REG:
278 printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
279 break;
280 case X86_OP_IMM:
281 printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
282 break;
283 case X86_OP_MEM:
284 printf("\t\toperands[%u].type: MEM\n", i);
285 if (op->mem.segment != X86_REG_INVALID)
286 printf("\t\t\toperands[%u].mem.segment: REG = %s\n", i, cs_reg_name(handle, op->mem.segment));
287 if (op->mem.base != X86_REG_INVALID)
288 printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base));
289 if (op->mem.index != X86_REG_INVALID)
290 printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index));
291 if (op->mem.scale != 1)
292 printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale);
293 if (op->mem.disp != 0)
294 printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp);
295 break;
296 default:
297 break;
298 }
299
300 // AVX broadcast type
301 if (op->avx_bcast != X86_AVX_BCAST_INVALID)
302 printf("\t\toperands[%u].avx_bcast: %u\n", i, op->avx_bcast);
303
304 // AVX zero opmask {z}
305 if (op->avx_zero_opmask != false)
306 printf("\t\toperands[%u].avx_zero_opmask: TRUE\n", i);
307
308 printf("\t\toperands[%u].size: %u\n", i, op->size);
309
310 switch(op->access) {
311 default:
312 break;
313 case CS_AC_READ:
314 printf("\t\toperands[%u].access: READ\n", i);
315 break;
316 case CS_AC_WRITE:
317 printf("\t\toperands[%u].access: WRITE\n", i);
318 break;
319 case CS_AC_READ | CS_AC_WRITE:
320 printf("\t\toperands[%u].access: READ | WRITE\n", i);
321 break;
322 }
323 }
324
325 // Print out all registers accessed by this instruction (either implicit or explicit)
326 if (!cs_regs_access(ud, ins,
327 regs_read, ®s_read_count,
328 regs_write, ®s_write_count)) {
329 if (regs_read_count) {
330 printf("\tRegisters read:");
331 for(i = 0; i < regs_read_count; i++) {
332 printf(" %s", cs_reg_name(handle, regs_read[i]));
333 }
334 printf("\n");
335 }
336
337 if (regs_write_count) {
338 printf("\tRegisters modified:");
339 for(i = 0; i < regs_write_count; i++) {
340 printf(" %s", cs_reg_name(handle, regs_write[i]));
341 }
342 printf("\n");
343 }
344 }
345
346 if (x86->eflags || x86->fpu_flags) {
347 for(i = 0; i < ins->detail->groups_count; i++) {
348 if (ins->detail->groups[i] == X86_GRP_FPU) {
349 printf("\tFPU_FLAGS:");
350 for(i = 0; i <= 63; i++)
351 if (x86->fpu_flags & ((uint64_t)1 << i)) {
352 printf(" %s", get_fpu_flag_name((uint64_t)1 << i));
353 }
354 printf("\n");
355 break;
356 }
357 }
358
359 if (i == ins->detail->groups_count) {
360 printf("\tEFLAGS:");
361 for(i = 0; i <= 63; i++)
362 if (x86->eflags & ((uint64_t)1 << i)) {
363 printf(" %s", get_eflag_name((uint64_t)1 << i));
364 }
365 printf("\n");
366 }
367 }
368
369 printf("\n");
370 }
371
test()372 static void test()
373 {
374 //#define X86_CODE32 "\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x78\x56\x00\x00"
375 //#define X86_CODE32 "\x05\x78\x56\x00\x00"
376 //#define X86_CODE32 "\x01\xd8"
377 //#define X86_CODE32 "\x05\x23\x01\x00\x00"
378 //#define X86_CODE32 "\x8d\x87\x89\x67\x00\x00"
379 //#define X86_CODE32 "\xa1\x13\x48\x6d\x3a\x8b\x81\x23\x01\x00\x00\x8b\x84\x39\x23\x01\x00\x00"
380 //#define X86_CODE32 "\xb4\xc6" // mov ah, 0x6c
381 //#define X86_CODE32 "\x77\x04" // ja +6
382 #define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00\xe9\xea\xbe\xad\xde\xff\x25\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff"
383 //#define X86_CODE64 "\xe9\x79\xff\xff\xff" // jmp 0xf7e
384
385 #define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\x66\xe9\xb8\x00\x00\x00\x67\xff\xa0\x23\x01\x00\x00\x66\xe8\xcb\x00\x00\x00\x74\xfc"
386 #define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\xe9\xea\xbe\xad\xde\xff\xa0\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff"
387 //#define X86_CODE32 "\x05\x23\x01\x00\x00\x0f\x01\xda"
388 //#define X86_CODE32 "\x0f\xa7\xc0" // xstorerng
389 //#define X86_CODE32 "\x64\xa1\x18\x00\x00\x00" // mov eax, dword ptr fs:[18]
390 //#define X86_CODE32 "\x64\xa3\x00\x00\x00\x00" // mov [fs:0x0], eax
391 //#define X86_CODE32 "\xd1\xe1" // shl ecx, 1
392 //#define X86_CODE32 "\xd1\xc8" // ror eax, 1
393 //#define X86_CODE32 "\x83\xC0\x80" // add eax, -x80
394 //#define X86_CODE32 "\xe8\x26\xfe\xff\xff" // call 0xe2b
395 //#define X86_CODE32 "\xcd\x80" // int 0x80
396 //#define X86_CODE32 "\x24\xb8" // and $0xb8,%al
397 //#define X86_CODE32 "\xf0\x01\xd8" // lock add eax,ebx
398 //#define X86_CODE32 "\xf3\xaa" // rep stosb
399 //#define X86_CODE32 "\x81\xc6\x23\x01\x00\x00"
400
401 struct platform platforms[] = {
402 {
403 CS_ARCH_X86,
404 CS_MODE_16,
405 (unsigned char *)X86_CODE16,
406 sizeof(X86_CODE16) - 1,
407 "X86 16bit (Intel syntax)"
408 },
409 {
410 CS_ARCH_X86,
411 CS_MODE_32,
412 (unsigned char *)X86_CODE32,
413 sizeof(X86_CODE32) - 1,
414 "X86 32 (AT&T syntax)",
415 CS_OPT_SYNTAX,
416 CS_OPT_SYNTAX_ATT,
417 },
418 {
419 CS_ARCH_X86,
420 CS_MODE_32,
421 (unsigned char *)X86_CODE32,
422 sizeof(X86_CODE32) - 1,
423 "X86 32 (Intel syntax)"
424 },
425 {
426 CS_ARCH_X86,
427 CS_MODE_64,
428 (unsigned char *)X86_CODE64,
429 sizeof(X86_CODE64) - 1,
430 "X86 64 (Intel syntax)"
431 },
432 };
433
434 uint64_t address = 0x1000;
435 cs_insn *insn;
436 int i;
437 size_t count;
438
439 for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
440 cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
441 if (err) {
442 printf("Failed on cs_open() with error returned: %u\n", err);
443 abort();
444 }
445
446 if (platforms[i].opt_type)
447 cs_option(handle, platforms[i].opt_type, platforms[i].opt_value);
448
449 cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
450
451 count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
452 if (count) {
453 size_t j;
454
455 printf("****************\n");
456 printf("Platform: %s\n", platforms[i].comment);
457 print_string_hex("Code:", platforms[i].code, platforms[i].size);
458 printf("Disasm:\n");
459
460 for (j = 0; j < count; j++) {
461 printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
462 print_insn_detail(handle, platforms[i].mode, &insn[j]);
463 }
464 printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
465
466 // free memory allocated by cs_disasm()
467 cs_free(insn, count);
468 } else {
469 printf("****************\n");
470 printf("Platform: %s\n", platforms[i].comment);
471 print_string_hex("Code:", platforms[i].code, platforms[i].size);
472 printf("ERROR: Failed to disasm given code!\n");
473 abort();
474 }
475
476 printf("\n");
477
478 cs_close(&handle);
479 }
480 }
481
main()482 int main()
483 {
484 test();
485
486 return 0;
487 }
488