1 /*
2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <drivers/arm/gicv3.h>
12 #include <common/interrupt_props.h>
13 #include <plat/common/platform.h>
14
15 #include "uniphier.h"
16
17 static uintptr_t uniphier_rdistif_base_addrs[PLATFORM_CORE_COUNT];
18
19 static const interrupt_prop_t uniphier_interrupt_props[] = {
20 /* G0 interrupts */
21
22 /* SGI0 */
23 INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
24 GIC_INTR_CFG_EDGE),
25 /* SGI6 */
26 INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
27 GIC_INTR_CFG_EDGE),
28
29 /* G1S interrupts */
30
31 /* Timer */
32 INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
33 GIC_INTR_CFG_LEVEL),
34 /* SGI1 */
35 INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
36 GIC_INTR_CFG_EDGE),
37 /* SGI2 */
38 INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
39 GIC_INTR_CFG_EDGE),
40 /* SGI3 */
41 INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
42 GIC_INTR_CFG_EDGE),
43 /* SGI4 */
44 INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
45 GIC_INTR_CFG_EDGE),
46 /* SGI5 */
47 INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
48 GIC_INTR_CFG_EDGE),
49 /* SGI7 */
50 INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
51 GIC_INTR_CFG_EDGE)
52 };
53
uniphier_mpidr_to_core_pos(u_register_t mpidr)54 static unsigned int uniphier_mpidr_to_core_pos(u_register_t mpidr)
55 {
56 return plat_core_pos_by_mpidr(mpidr);
57 }
58
59 static const struct gicv3_driver_data uniphier_gic_driver_data[] = {
60 [UNIPHIER_SOC_LD11] = {
61 .gicd_base = 0x5fe00000,
62 .gicr_base = 0x5fe40000,
63 .interrupt_props = uniphier_interrupt_props,
64 .interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props),
65 .rdistif_num = PLATFORM_CORE_COUNT,
66 .rdistif_base_addrs = uniphier_rdistif_base_addrs,
67 .mpidr_to_core_pos = uniphier_mpidr_to_core_pos,
68 },
69 [UNIPHIER_SOC_LD20] = {
70 .gicd_base = 0x5fe00000,
71 .gicr_base = 0x5fe80000,
72 .interrupt_props = uniphier_interrupt_props,
73 .interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props),
74 .rdistif_num = PLATFORM_CORE_COUNT,
75 .rdistif_base_addrs = uniphier_rdistif_base_addrs,
76 .mpidr_to_core_pos = uniphier_mpidr_to_core_pos,
77 },
78 [UNIPHIER_SOC_PXS3] = {
79 .gicd_base = 0x5fe00000,
80 .gicr_base = 0x5fe80000,
81 .interrupt_props = uniphier_interrupt_props,
82 .interrupt_props_num = ARRAY_SIZE(uniphier_interrupt_props),
83 .rdistif_num = PLATFORM_CORE_COUNT,
84 .rdistif_base_addrs = uniphier_rdistif_base_addrs,
85 .mpidr_to_core_pos = uniphier_mpidr_to_core_pos,
86 },
87 };
88
uniphier_gic_driver_init(unsigned int soc)89 void uniphier_gic_driver_init(unsigned int soc)
90 {
91 assert(soc < ARRAY_SIZE(uniphier_gic_driver_data));
92
93 gicv3_driver_init(&uniphier_gic_driver_data[soc]);
94 }
95
uniphier_gic_init(void)96 void uniphier_gic_init(void)
97 {
98 gicv3_distif_init();
99 gicv3_rdistif_init(plat_my_core_pos());
100 gicv3_cpuif_enable(plat_my_core_pos());
101 }
102
uniphier_gic_cpuif_enable(void)103 void uniphier_gic_cpuif_enable(void)
104 {
105 gicv3_cpuif_enable(plat_my_core_pos());
106 }
107
uniphier_gic_cpuif_disable(void)108 void uniphier_gic_cpuif_disable(void)
109 {
110 gicv3_cpuif_disable(plat_my_core_pos());
111 }
112
uniphier_gic_pcpu_init(void)113 void uniphier_gic_pcpu_init(void)
114 {
115 gicv3_rdistif_init(plat_my_core_pos());
116 }
117