Searched refs:TR (Results 1 – 14 of 14) sorted by relevance
| /art/disassembler/ |
| D | disassembler_arm64.cc | 37 TR = 19, enumerator
48 if (reg.GetCode() == TR) { in AppendRegisterNameToOutput()
103 if (instr->GetRn() == TR) { in VisitLoadStoreUnsignedOffset()
116 target->GetRn() == TR && in VisitUnconditionalBranch()
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| D | disassembler_arm.cc | 40 static const vixl::aarch32::Register tr(TR);
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| /art/cmdline/detail/ |
| D | cmdline_parser_detail.h | 54 template <typename TL, typename TR>
55 static std::true_type EqualityOperatorTest(const TL& left, const TR& right,
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| /art/compiler/utils/arm64/ |
| D | jni_macro_assembler_arm64.cc | 55 ___ Mov(reg_x(dest.AsArm64().AsXRegister()), reg_x(TR)); in GetCurrentThread()
59 StoreToOffset(TR, SP, offset.Int32Value()); in GetCurrentThread()
176 ___ Str(scratch, MEM_OP(reg_x(TR), tr_offs.Int32Value())); in StoreStackOffsetToThread()
183 ___ Str(scratch, MEM_OP(reg_x(TR), tr_offs.Int32Value())); in StoreStackPointerToThread()
286 return Load(m_dst.AsArm64(), TR, src.Int32Value(), size); in LoadFromThread()
325 LoadFromOffset(dst.AsXRegister(), TR, offs.Int32Value()); in LoadRawPtrFromThread()
456 ___ Ldr(scratch, MEM_OP(reg_x(TR), tr_offs.Int32Value())); in CopyRawPtrFromThread()
466 StoreToOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value()); in CopyRawPtrToThread()
706 ___ Ldr(scratch, MEM_OP(reg_x(TR), Thread::ExceptionOffset<kArm64PointerSize>().Int32Value())); in ExceptionPoll()
736 ___ Ldr(test_reg, MEM_OP(reg_x(TR), is_gc_marking_offset)); in TestGcMarking()
[all …]
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| D | assembler_arm64.cc | 195 vixl::aarch64::Register tr = reg_x(TR); // Thread Register. in GenerateMarkingRegisterCheck()
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| D | managed_register_arm64_test.cc | 627 EXPECT_TRUE(vixl::aarch64::x19.Is(Arm64Assembler::reg_x(TR))); in TEST()
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| /art/runtime/arch/arm/ |
| D | registers_arm.h | 44 TR = 9, // ART Thread Register enumerator
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| D | context_arm.cc | 112 DCHECK_EQ(reinterpret_cast<uintptr_t>(Thread::Current()), gprs[TR]); in DoLongJump()
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| /art/runtime/arch/arm64/ |
| D | registers_arm64.h | 63 TR = X19, // ART Thread Register - Managed Runtime (Callee Saved Reg) enumerator
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| D | context_arm64.cc | 147 DCHECK_EQ(reinterpret_cast<uintptr_t>(Thread::Current()), gprs[TR]); in DoLongJump()
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| /art/compiler/trampolines/ |
| D | trampoline_compiler.cc | 113 __ JumpTo(Arm64ManagedRegister::FromXRegister(TR), Offset(offset.Int32Value()), in CreateTrampoline()
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| /art/compiler/utils/arm/ |
| D | assembler_arm_vixl.cc | 39 extern const vixl32::Register tr(TR);
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| /art/compiler/optimizing/ |
| D | code_generator_arm64.cc | 5128 assembler.JumpTo(ManagedRegister(arm64::TR), offset, ManagedRegister(arm64::IP0)); in EmitThunkCode()
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| D | code_generator_arm_vixl.cc | 2068 blocked_core_registers_[TR] = true; in SetupBlockedRegisters()
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