Home
last modified time | relevance | path

Searched refs:lr (Results 1 – 25 of 34) sorted by relevance

12

/art/runtime/arch/arm/
Dmemcmp16_arm.S39 bxeq lr
61 bxne lr
64 bx lr
68 0: push {r4, lr}
71 .cfi_rel_offset lr, 4
82 popne {r4, lr}
83 bxne lr
109 ldr lr, [r1, #4]!
113 eorseq r0, r0, lr
115 ldreq lr, [r1, #4]!
[all …]
Djni_entrypoints_arm.S25 push {r0, r1, r2, r3, lr} @ spill regs
27 .cfi_rel_offset lr, 16
50 pop {r0, r1, r2, r3, lr} @ restore regs
52 .cfi_restore lr
84 ldr lr, [sp, #20]
90 ldrd ip, lr, [r4, #FRAME_SIZE_SAVE_REFS_AND_ARGS]
92 strd ip, lr, [r4], #8
106 stmia ip, {r1-r3, r5-r8, r10-r11, lr} // LR: Save return address for tail call from JNI stub.
120 pop {r1, lr}
122 .cfi_restore lr
[all …]
Dquick_entrypoints_arm.S70 push {r0-r12, lr} @ 14 words of callee saves and args.
85 .cfi_rel_offset lr, 52
94 pop {r0-r12, lr} @ 14 words of callee saves
108 .cfi_restore lr
464 str lr, [sp, r10] @ Store link register per the compiler ABI
483 ldr lr, [sp, #56] @ Load LR from gprs_, 56 = 4 * 14.
516 bx lr
596 bx lr
627 push {r0-r2, lr} @ save arguments, padding (r2) and link register
632 .cfi_rel_offset lr, 12
[all …]
Dasm_support_arm.S242 push {r1-r3, r5-r8, r10-r11, lr} @ 10 words of callee saves and args.
253 .cfi_rel_offset lr, 36
272 pop {r1-r3, r5-r8, r10-r11, lr} @ 10 words of callee saves and args.
282 .cfi_restore lr
290 push {r4-r11, lr} @ 9 words (36 bytes) of callee saves.
300 .cfi_rel_offset lr, 32
346 bx lr
359 bx lr
372 push {r5-r8, r10-r11, lr} @ 7 words of callee saves
380 .cfi_rel_offset lr, 24
[all …]
Dinstruction_set_features_assembly_tests.S41 bx lr
64 bx lr
/art/runtime/interpreter/mterp/armng/
Dmain.S341 ldrh lr, [\code_item, #COMPACT_CODE_ITEM_FIELDS_OFFSET]
342 ubfx \registers, lr, #COMPACT_CODE_ITEM_REGISTERS_SIZE_SHIFT, #4
343 ubfx \outs, lr, #COMPACT_CODE_ITEM_OUTS_SIZE_SHIFT, #4
345 ubfx \ins, lr, #COMPACT_CODE_ITEM_INS_SIZE_SHIFT, #4
347 ubfx ip, lr, #COMPACT_CODE_ITEM_INS_SIZE_SHIFT, #4
351 ldrh lr, [\code_item, #COMPACT_CODE_ITEM_FLAGS_OFFSET]
352 tst lr, #COMPACT_CODE_ITEM_REGISTERS_INS_OUTS_FLAGS
355 tst lr, #COMPACT_CODE_ITEM_INSNS_FLAG
359 tst lr, #COMPACT_CODE_ITEM_REGISTERS_FLAG
361 ldrh lr, [ip, #-2]!
[all …]
Darithmetic.S166 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs
201 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
269 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
292 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
552 umull r0, lr, r2, r0 @ r0/lr <- ZxX RdLo == Rn - this is OK.
555 add r1, r3, lr @ r1<- lr + low(ZxW + (YxX))
556 CLEAR_SHADOW_PAIR r4, lr, ip @ Zero out the shadow regs
580 umull r0, lr, r2, r0 @ r0/lr <- ZxX RdLo == Rn - this is OK.
584 add r1, r3, lr @ r1<- lr + low(ZxW + (YxX))
790 CLEAR_SHADOW_PAIR r4, lr, ip @ Zero out the shadow regs
[all …]
Dother.S108 CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs
121 CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs
256 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
270 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
282 VREG_INDEX_TO_ADDR lr, r2 @ r2<- &fp[AAAA]
286 SET_VREG_WIDE_BY_ADDR r0, r1, lr @ fp[AAAA]<- r0/r1
298 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
Dobject.S83 CLEAR_SHADOW_PAIR r2, ip, lr
124 CLEAR_SHADOW_PAIR r2, ip, lr
267 CLEAR_SHADOW_PAIR r2, ip, lr
314 CLEAR_SHADOW_PAIR r2, ip, lr
446 ldr lr, [rSELF, #THREAD_ALLOC_OBJECT_ENTRYPOINT_OFFSET]
447 blx lr
Dfloating_point.S22 SET_VREG_FLOAT s2, r4, lr @ vAA<- s2
/art/runtime/arch/arm64/
Djni_entrypoints_arm64.S110 stp x15, lr, [sp, #128]
111 .cfi_rel_offset lr, 136
115 mov x1, lr // x1 := caller_pc
129 ldp x15, lr, [sp, #128]
130 .cfi_restore lr
145 mov xIP1, lr
194 str lr, [x29, #__SIZEOF_POINTER__]
203 str lr, [x29, #(FRAME_SIZE_SAVE_REFS_AND_ARGS - __SIZEOF_POINTER__)]
232 RESTORE_REG_BASE x29, lr, __SIZEOF_POINTER__
319 str lr, [x29, #__SIZEOF_POINTER__]
/art/runtime/interpreter/mterp/arm/
Dcontrol_flow.S147 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
149 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
162 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
164 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
177 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
179 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
Dfloating_point.S22 SET_VREG_FLOAT s2, r9, lr @ vAA<- s2
352 bx lr @ return
392 bx lr @ return
Darithmetic.S166 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs
201 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
269 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
292 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
547 umull r1, lr, r2, r0 @ r1/lr <- ZxX
550 add r2, r2, lr @ r2<- lr + low(ZxW + (YxX))
551 CLEAR_SHADOW_PAIR r0, lr, ip @ Zero out the shadow regs
575 umull r1, lr, r2, r0 @ r1/lr <- ZxX
579 add r2, r2, lr @ r2<- r2 + low(ZxW + (YxX))
785 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs
[all …]
Dother.S116 CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs
129 CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs
280 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
294 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
306 VREG_INDEX_TO_ADDR lr, r2 @ r2<- &fp[AAAA]
310 SET_VREG_WIDE_BY_ADDR r0, r1, lr @ fp[AAAA]<- r0/r1
322 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
Dmain.S385 stmfd sp!, {r3-r10,fp,lr} @ save 10 regs, (r3 just to align 64)
396 .cfi_rel_offset lr, 36
/art/runtime/interpreter/mterp/arm64/
Dmain.S408 SAVE_TWO_REGS fp, lr, 64
606 ldr lr, [xSELF, #THREAD_FLAGS_OFFSET]
610 ands lr, lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
748 RESTORE_TWO_REGS fp, lr, 64
766 RESTORE_TWO_REGS fp, lr, 64
/art/compiler/utils/arm/
Djni_macro_assembler_arm_vixl.cc101 if (core_spill_mask == (1u << lr.GetCode()) && in BuildFrame()
110 cfi().RelOffset(DWARFReg(lr), kFramePointerSize); in BuildFrame()
160 if ((core_spill_mask & (1u << lr.GetCode())) != 0u && !emit_code_before_return) { in RemoveFrame()
162 core_spill_mask ^= (1u << lr.GetCode()) | (1u << pc.GetCode()); in RemoveFrame()
247 ___ Bx(vixl32::lr); in RemoveFrame()
941 asm_.LoadFromOffset(kLoadWord, lr, base, offset.Int32Value()); in Call()
942 ___ Blx(lr); in Call()
948 asm_.LoadFromOffset(kLoadWord, lr, sp, base.Int32Value()); in Call()
949 asm_.LoadFromOffset(kLoadWord, lr, lr, offset.Int32Value()); in Call()
950 ___ Blx(lr); in Call()
[all …]
/art/runtime/interpreter/mterp/arm64ng/
Dmain.S469 RESTORE_TWO_REGS x29, lr, 144
922 ldr lr, [x0, #ART_METHOD_QUICK_CODE_OFFSET_64]
923 blr lr
964 ldr lr, [x0, #ART_METHOD_QUICK_CODE_OFFSET_64]
965 blr lr
1027 ldr lr, [x0, #ART_METHOD_QUICK_CODE_OFFSET_64]
1028 blr lr
1272 ldr lr, [x0, #ART_METHOD_QUICK_CODE_OFFSET_64]
1273 blr lr
1309 ldr lr, [x0, #ART_METHOD_QUICK_CODE_OFFSET_64]
[all …]
Dobject.S389 ldr lr, [xSELF, #THREAD_ALLOC_OBJECT_ENTRYPOINT_OFFSET]
390 blr lr
/art/compiler/utils/arm64/
Djni_macro_assembler_arm64.cc638 ___ Ldr(lr, MEM_OP(reg_x(base.AsXRegister()), offs.Int32Value())); in Call()
639 ___ Blr(lr); in Call()
644 ___ Ldr(lr, MEM_OP(reg_x(SP), base.Int32Value())); in Call()
645 ___ Ldr(lr, MEM_OP(lr, offs.Int32Value())); in Call()
646 ___ Blr(lr); in Call()
768 ___ Ldr(lr, in EmitExceptionPoll()
772 ___ Blr(lr); in EmitExceptionPoll()
/art/compiler/utils/
Dassembler_thumb_test_expected.cc.inc2 " 0: 2d e9 e0 4d push.w {r5, r6, r7, r8, r10, r11, lr}\n"
44 " 8a: d0 f8 30 e0 ldr.w lr, [r0, #48]\n"
45 " 8e: f0 47 blx lr\n"
152 " 218: bd e8 e0 4d pop.w {r5, r6, r7, r8, r10, r11, lr}\n"
154 " 220: 70 47 bx lr\n"
156 " 224: d9 f8 e0 e2 ldr.w lr, [r9, #736]\n"
157 " 228: f0 47 blx lr\n"
/art/compiler/optimizing/
Doptimizing_cfi_test_expected.inc11 // 0x00000000: push {r5, r6, lr}
47 // 0x00000008: stp x22, lr, [sp, #48]
59 // 0x00000018: ldp x22, lr, [sp, #48]
163 // 0x00000000: push {r5, r6, lr}
Dcode_generator_arm64.cc936 AddAllocatedRegister(LocationFrom(lr)); in CodeGeneratorARM64()
1149 __ Stp(kArtMethodRegister, lr, MemOperand(sp, 0)); in MaybeIncrementHotness()
1158 __ Ldr(lr, MemOperand(tr, entrypoint_offset)); in MaybeIncrementHotness()
1161 __ Blr(lr); in MaybeIncrementHotness()
1164 __ Ldr(lr, MemOperand(sp, 8)); in MaybeIncrementHotness()
1816 __ Ldr(lr, MemOperand(tr, entrypoint_offset.Int32Value())); in InvokeRuntime()
1819 __ blr(lr); in InvokeRuntime()
1837 __ Ldr(lr, MemOperand(tr, entry_point_offset)); in InvokeRuntimeWithoutRecordingPcInfo()
1838 __ Blr(lr); in InvokeRuntimeWithoutRecordingPcInfo()
4474 __ Ldr(lr, MemOperand(temp, entry_point.Int32Value())); in VisitInvokeInterface()
[all …]
/art/compiler/jni/
Djni_cfi_test_expected.inc21 // 0x00000000: push {r5,r6,r7,r8,r10,r11,lr}
80 // 0x00000020: pop {r5,r6,r7,r8,r10,r11,lr}
90 // 0x00000028: bx lr
136 // 0x00000018: stp x29, lr, [sp, #160]
176 // 0x0000005c: ldp x29, lr, [sp, #160]

12