| /art/test/434-shifter-operand/ |
| D | Android.bp | 3 // Build rules for ART run-test `434-shifter-operand`.
16 name: "art-run-test-434-shifter-operand",
21 ":art-run-test-434-shifter-operand-expected-stdout",
22 ":art-run-test-434-shifter-operand-expected-stderr",
28 name: "art-run-test-434-shifter-operand-expected-stdout",
29 out: ["art-run-test-434-shifter-operand-expected-stdout.txt"],
36 name: "art-run-test-434-shifter-operand-expected-stderr",
37 out: ["art-run-test-434-shifter-operand-expected-stderr.txt"],
|
| /art/test/551-checker-shifter-operand/ |
| D | Android.bp | 3 // Build rules for ART run-test `551-checker-shifter-operand`.
16 name: "art-run-test-551-checker-shifter-operand",
21 ":art-run-test-551-checker-shifter-operand-expected-stdout",
22 ":art-run-test-551-checker-shifter-operand-expected-stderr",
31 name: "art-run-test-551-checker-shifter-operand-expected-stdout",
32 out: ["art-run-test-551-checker-shifter-operand-expected-stdout.txt"],
39 name: "art-run-test-551-checker-shifter-operand-expected-stderr",
40 out: ["art-run-test-551-checker-shifter-operand-expected-stderr.txt"],
|
| D | info.txt | 1 Test the merging of instructions into the shifter operand on arm64.
|
| /art/disassembler/ |
| D | disassembler_arm.cc | 101 DisassemblerStream& operator<<(const MemOperand& operand) override { in operator <<() argument
104 DCHECK(!operand.GetBaseRegister().Is(pc)); in operator <<()
105 DisassemblerStream::operator<<(operand); in operator <<()
107 if (operand.GetBaseRegister().Is(tr) && operand.IsImmediate()) { in operator <<()
109 options_->thread_offset_name_function_(os(), operand.GetOffsetImmediate()); in operator <<()
115 DisassemblerStream& operator<<(const vixl::aarch32::AlignedMemOperand& operand) override { in operator <<() argument
118 DCHECK(!operand.GetBaseRegister().Is(pc)); in operator <<()
119 return DisassemblerStream::operator<<(operand); in operator <<()
|
| /art/compiler/utils/arm/ |
| D | assembler_arm_vixl.h | 86 void (func_name)(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { \
87 MacroAssembler::func_name(vixl32::DontCare, rd, rn, operand); \
111 void (func_name)(vixl32::Register rd, const vixl32::Operand& operand) { \
112 MacroAssembler::func_name(vixl32::DontCare, rd, operand); \
134 void Add(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { in Add() argument
135 if (rd.Is(rn) && operand.IsPlainRegister()) { in Add()
136 MacroAssembler::Add(rd, rn, operand); in Add()
138 MacroAssembler::Add(vixl32::DontCare, rd, rn, operand); in Add()
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| /art/test/550-checker-multiply-accumulate/ |
| D | info.txt | 1 Test the merging of instructions into the shifter operand on arm64.
|
| /art/compiler/utils/x86_64/ |
| D | assembler_x86_64.h | 807 void shll(CpuRegister operand, CpuRegister shifter);
809 void shrl(CpuRegister operand, CpuRegister shifter);
811 void sarl(CpuRegister operand, CpuRegister shifter);
814 void shlq(CpuRegister operand, CpuRegister shifter);
816 void shrq(CpuRegister operand, CpuRegister shifter);
818 void sarq(CpuRegister operand, CpuRegister shifter);
878 void rorl(CpuRegister operand, CpuRegister shifter);
880 void roll(CpuRegister operand, CpuRegister shifter);
883 void rorq(CpuRegister operand, CpuRegister shifter);
885 void rolq(CpuRegister operand, CpuRegister shifter);
[all …]
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| D | assembler_x86_64.cc | 4539 void X86_64Assembler::shll(CpuRegister operand, CpuRegister shifter) { in shll() argument
4540 EmitGenericShift(false, 4, operand, shifter); in shll()
4544 void X86_64Assembler::shlq(CpuRegister operand, CpuRegister shifter) { in shlq() argument
4545 EmitGenericShift(true, 4, operand, shifter); in shlq()
4559 void X86_64Assembler::shrl(CpuRegister operand, CpuRegister shifter) { in shrl() argument
4560 EmitGenericShift(false, 5, operand, shifter); in shrl()
4564 void X86_64Assembler::shrq(CpuRegister operand, CpuRegister shifter) { in shrq() argument
4565 EmitGenericShift(true, 5, operand, shifter); in shrq()
4574 void X86_64Assembler::sarl(CpuRegister operand, CpuRegister shifter) { in sarl() argument
4575 EmitGenericShift(false, 7, operand, shifter); in sarl()
[all …]
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| /art/test/162-method-resolution/jasmin/ |
| D | Test5User.j | 30 dup ; Bogus operand to be swallowed by the pop in the non-exceptional path.
34 pop ; Pops the exception or the bogus operand from above.
|
| /art/compiler/utils/x86/ |
| D | assembler_x86.cc | 3330 void X86Assembler::shll(Register operand, Register shifter) { in shll() argument
3331 EmitGenericShift(4, Operand(operand), shifter); in shll()
3350 void X86Assembler::shrl(Register operand, Register shifter) { in shrl() argument
3351 EmitGenericShift(5, Operand(operand), shifter); in shrl()
3370 void X86Assembler::sarl(Register operand, Register shifter) { in sarl() argument
3371 EmitGenericShift(7, Operand(operand), shifter); in sarl()
3426 void X86Assembler::roll(Register operand, Register shifter) { in roll() argument
3427 EmitGenericShift(0, Operand(operand), shifter); in roll()
3436 void X86Assembler::rorl(Register operand, Register shifter) { in rorl() argument
3437 EmitGenericShift(1, Operand(operand), shifter); in rorl()
[all …]
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| D | assembler_x86.h | 384 void rorl(Register operand, Register shifter);
386 void roll(Register operand, Register shifter);
780 void shll(Register operand, Register shifter);
784 void shrl(Register operand, Register shifter);
788 void sarl(Register operand, Register shifter);
977 void EmitOperand(int rm, const Operand& operand);
980 int rm, const Operand& operand, const Immediate& immediate, bool is_16_op = false);
985 void EmitGenericShift(int rm, const Operand& operand, const Immediate& imm);
986 void EmitGenericShift(int rm, const Operand& operand, Register shifter);
991 X86ManagedRegister operand,
[all …]
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| /art/runtime/interpreter/mterp/armng/ |
| D | arithmetic.S | 25 cmp r1, #0 @ is second operand zero?
58 cmp r1, #0 @ is second operand zero?
89 cmp r1, #0 @ is second operand zero?
125 @cmp r1, #0 @ is second operand zero?
381 cmp r1, #0 @ is second operand zero?
410 cmp r1, #0 @ is second operand zero?
440 cmp r1, #0 @ is second operand zero?
470 @cmp r1, #0 @ is second operand zero?
638 cmp r1, #0 @ is second operand zero?
670 cmp r1, #0 @ is second operand zero?
[all …]
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| /art/runtime/interpreter/mterp/arm/ |
| D | arithmetic.S | 25 cmp r1, #0 @ is second operand zero?
58 cmp r1, #0 @ is second operand zero?
89 cmp r1, #0 @ is second operand zero?
125 @cmp r1, #0 @ is second operand zero?
378 cmp r1, #0 @ is second operand zero?
407 cmp r1, #0 @ is second operand zero?
437 cmp r1, #0 @ is second operand zero?
467 @cmp r1, #0 @ is second operand zero?
633 cmp r1, #0 @ is second operand zero?
665 cmp r1, #0 @ is second operand zero?
[all …]
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| /art/compiler/optimizing/ |
| D | loop_optimization.cc | 88 /*out*/ HInstruction** operand);
94 /*out*/ HInstruction** operand) { in IsSignExtensionAndGet() argument
104 *operand = instruction; in IsSignExtensionAndGet()
111 *operand = instruction; in IsSignExtensionAndGet()
124 *operand = instruction; in IsSignExtensionAndGet()
140 *operand = conv; in IsSignExtensionAndGet()
147 IsZeroExtensionAndGet(instruction->InputAt(0), type, /*out*/ operand); in IsSignExtensionAndGet()
159 /*out*/ HInstruction** operand) { in IsZeroExtensionAndGet() argument
169 *operand = instruction; in IsZeroExtensionAndGet()
176 *operand = instruction; in IsZeroExtensionAndGet()
[all …]
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| D | code_generator_arm_vixl.cc | 1752 Operand operand(0); in GenerateConditionIntegralOrNonPrimitive() local
1755 operand = Operand::From(value); in GenerateConditionIntegralOrNonPrimitive()
1758 operand = InputOperandAt(cond, 0); in GenerateConditionIntegralOrNonPrimitive()
1761 operand = InputOperandAt(cond, 1); in GenerateConditionIntegralOrNonPrimitive()
1765 __ Subs(out, in, operand); in GenerateConditionIntegralOrNonPrimitive()
1775 __ Sub(out, in, operand); in GenerateConditionIntegralOrNonPrimitive()
|
| /art/ |
| D | TEST_MAPPING | 485 "name": "art-run-test-434-shifter-operand[com.google.android.art.apex]"
1672 "name": "art-run-test-434-shifter-operand"
|