Searched refs:reg_d (Results 1 – 3 of 3) sorted by relevance
672 EXPECT_TRUE(vixl::aarch64::d0.Is(Arm64Assembler::reg_d(D0))); in TEST()673 EXPECT_TRUE(vixl::aarch64::d1.Is(Arm64Assembler::reg_d(D1))); in TEST()674 EXPECT_TRUE(vixl::aarch64::d2.Is(Arm64Assembler::reg_d(D2))); in TEST()675 EXPECT_TRUE(vixl::aarch64::d3.Is(Arm64Assembler::reg_d(D3))); in TEST()676 EXPECT_TRUE(vixl::aarch64::d4.Is(Arm64Assembler::reg_d(D4))); in TEST()677 EXPECT_TRUE(vixl::aarch64::d5.Is(Arm64Assembler::reg_d(D5))); in TEST()678 EXPECT_TRUE(vixl::aarch64::d6.Is(Arm64Assembler::reg_d(D6))); in TEST()679 EXPECT_TRUE(vixl::aarch64::d7.Is(Arm64Assembler::reg_d(D7))); in TEST()680 EXPECT_TRUE(vixl::aarch64::d8.Is(Arm64Assembler::reg_d(D8))); in TEST()681 EXPECT_TRUE(vixl::aarch64::d9.Is(Arm64Assembler::reg_d(D9))); in TEST()[all …]
37 #define reg_d(D) Arm64Assembler::reg_d(D) macro131 ___ Str(reg_d(source), MEM_OP(reg_x(base), offset)); in StoreDToOffset()248 ___ Ldr(reg_d(dest), MEM_OP(reg_x(base), offset)); in LoadDFromOffset()275 ___ Ldr(reg_d(dest.AsDRegister()), MEM_OP(reg_x(base), offset)); in Load()423 CHECK(!temps.IsAvailable(reg_d(dst.AsDRegister()))); in Move()448 ___ Fmov(reg_d(dst.AsDRegister()), reg_d(src.AsDRegister())); in Move()789 fp_reg_list.Combine(reg_d(reg.AsDRegister()).GetCode()); in BuildFrame()825 fp_reg_list.Combine(reg_d(reg.AsDRegister()).GetCode()); in RemoveFrame()
183 static vixl::aarch64::VRegister reg_d(int code) { in reg_d() function