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Searched refs:root_reg (Results 1 – 8 of 8) sorted by relevance

/art/dex2oat/linker/arm/
Drelative_patcher_thumb2_test.cc289 static uint32_t EncodeBakerReadBarrierGcRootData(uint32_t root_reg, bool narrow) { in EncodeBakerReadBarrierGcRootData() argument
290 return arm::CodeGeneratorARMVIXL::EncodeBakerReadBarrierGcRootData(root_reg, narrow); in EncodeBakerReadBarrierGcRootData()
307 std::vector<uint8_t> CompileBakerGcRootThunk(uint32_t root_reg, bool narrow) { in CompileBakerGcRootThunk() argument
309 /* literal_offset */ 0u, EncodeBakerReadBarrierGcRootData(root_reg, narrow)); in CompileBakerGcRootThunk()
1188 for (uint32_t root_reg : kBakerValidRegs) { in TEST_F() local
1190 uint32_t ldr = kLdrWInsn | (/* offset */ 8) | (/* base_reg */ 0 << 16) | (root_reg << 12); in TEST_F()
1196 kLiteralOffset, EncodeBakerReadBarrierGcRootData(root_reg, /* narrow */ false)), in TEST_F()
1205 for (uint32_t root_reg : kBakerValidRegs) { in TEST_F() local
1208 uint32_t ldr = kLdrWInsn | (/* offset */ 8) | (/* base_reg */ 0 << 16) | (root_reg << 12); in TEST_F()
1213 std::vector<uint8_t> expected_thunk = CompileBakerGcRootThunk(root_reg, /* narrow */ false); in TEST_F()
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/art/compiler/optimizing/
Dcode_generator_arm_vixl.h875 static uint32_t EncodeBakerReadBarrierGcRootData(uint32_t root_reg, bool narrow) { in EncodeBakerReadBarrierGcRootData() argument
876 CheckValidReg(root_reg); in EncodeBakerReadBarrierGcRootData()
877 DCHECK(!narrow || root_reg < 8u) << root_reg; in EncodeBakerReadBarrierGcRootData()
881 BakerReadBarrierFirstRegField::Encode(root_reg) | in EncodeBakerReadBarrierGcRootData()
886 static uint32_t EncodeBakerReadBarrierIntrinsicCasData(uint32_t root_reg) { in EncodeBakerReadBarrierIntrinsicCasData() argument
887 CheckValidReg(root_reg); in EncodeBakerReadBarrierIntrinsicCasData()
889 BakerReadBarrierFirstRegField::Encode(root_reg) | in EncodeBakerReadBarrierIntrinsicCasData()
Dcode_generator_arm64.h1021 static inline uint32_t EncodeBakerReadBarrierGcRootData(uint32_t root_reg) { in EncodeBakerReadBarrierGcRootData() argument
1022 CheckValidReg(root_reg); in EncodeBakerReadBarrierGcRootData()
1024 BakerReadBarrierFirstRegField::Encode(root_reg) | in EncodeBakerReadBarrierGcRootData()
Dcode_generator_arm64.cc1034 const uint32_t root_reg = BakerReadBarrierFirstRegField::Decode(encoded_data); in Finalize() local
1037 if ((prev_insn & 0xffe0ffff) != (0x2a0003e0 | root_reg)) { // MOV? in Finalize()
1038 CHECK_EQ(prev_insn & 0xffc0001fu, 0xb9400000u | root_reg); // LDR? in Finalize()
6472 Register root_reg = RegisterFrom(root, DataType::Type::kReference); in GenerateGcRootFieldLoad() local
6498 uint32_t custom_data = EncodeBakerReadBarrierGcRootData(root_reg.GetCode()); in GenerateGcRootFieldLoad()
6508 __ ldr(root_reg, MemOperand(obj.X(), offset)); in GenerateGcRootFieldLoad()
6516 __ Add(root_reg.X(), obj.X(), offset); in GenerateGcRootFieldLoad()
6518 EmitAddPlaceholder(fixup_label, root_reg.X(), obj.X()); in GenerateGcRootFieldLoad()
6527 __ Ldr(root_reg, MemOperand(obj, offset)); in GenerateGcRootFieldLoad()
6529 EmitLdrOffsetPlaceholder(fixup_label, root_reg, obj.X()); in GenerateGcRootFieldLoad()
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Dcode_generator_arm_vixl.cc2025 const uint32_t root_reg = BakerReadBarrierFirstRegField::Decode(encoded_data); in Finalize() local
2026 CHECK_EQ(prev_insn & 0xfff0f000u, 0xf8d00000u | (root_reg << 12)); in Finalize()
2030 const uint32_t root_reg = BakerReadBarrierFirstRegField::Decode(encoded_data); in Finalize() local
2033 if ((prev_insn & 0xff87u) != (0x4600 | root_reg)) { in Finalize()
2034 CHECK_EQ(prev_insn & 0xf807u, 0x6800u | root_reg); in Finalize()
2043 const uint32_t root_reg = BakerReadBarrierFirstRegField::Decode(encoded_data); in Finalize() local
2044 DCHECK_GE(root_reg, 8u); // Used only for high registers. in Finalize()
2045 CHECK_EQ(prev_insn & 0xfffffff0u, 0xea4f0000u | (root_reg << 8)); in Finalize()
8796 vixl32::Register root_reg = RegisterFrom(root); in GenerateGcRootFieldLoad() local
8820 bool narrow = CanEmitNarrowLdr(root_reg, obj, offset); in GenerateGcRootFieldLoad()
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Dcode_generator_x86_64.cc7381 CpuRegister root_reg = root.AsRegister<CpuRegister>(); in GenerateGcRootFieldLoad() local
7395 __ movl(root_reg, address); in GenerateGcRootFieldLoad()
7423 __ leaq(root_reg, address); in GenerateGcRootFieldLoad()
7433 __ movl(root_reg, address); in GenerateGcRootFieldLoad()
Dcode_generator_x86.cc8303 Register root_reg = root.AsRegister<Register>(); in GenerateGcRootFieldLoad() local
8317 __ movl(root_reg, address); in GenerateGcRootFieldLoad()
8345 __ leal(root_reg, address); in GenerateGcRootFieldLoad()
8355 __ movl(root_reg, address); in GenerateGcRootFieldLoad()
/art/dex2oat/linker/arm64/
Drelative_patcher_arm64_test.cc528 static uint32_t EncodeBakerReadBarrierGcRootData(uint32_t root_reg) { in EncodeBakerReadBarrierGcRootData() argument
529 return arm64::CodeGeneratorARM64::EncodeBakerReadBarrierGcRootData(root_reg); in EncodeBakerReadBarrierGcRootData()
544 std::vector<uint8_t> CompileBakerGcRootThunk(uint32_t root_reg) { in CompileBakerGcRootThunk() argument
546 /* literal_offset */ 0u, EncodeBakerReadBarrierGcRootData(root_reg)); in CompileBakerGcRootThunk()
1380 for (uint32_t root_reg : valid_regs) { in TEST_F() local
1382 uint32_t ldr = kLdrWInsn | (/* offset */ 8 << (10 - 2)) | (/* base_reg */ 0 << 5) | root_reg; in TEST_F()
1388 kLiteralOffset, EncodeBakerReadBarrierGcRootData(root_reg)), in TEST_F()
1397 for (uint32_t root_reg : valid_regs) { in TEST_F() local
1401 uint32_t ldr = kLdrWInsn | (/* offset */ 8 << (10 - 2)) | (/* base_reg */ 0 << 5) | root_reg; in TEST_F()
1406 std::vector<uint8_t> expected_thunk = CompileBakerGcRootThunk(root_reg); in TEST_F()
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