| /external/arm-trusted-firmware/docs/design/ |
| D | cpu-specific-build-macros.rst | 42 - `Cortex-A57 MPCore Software Developers Errata Notice`_
50 is for example ``A57`` for the ``Cortex_A57`` CPU.
156 For Cortex-A57, the following errata build flags are defined :
158 - ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
161 - ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57
164 - ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
167 - ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57
170 - ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57
173 - ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
176 - ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57
[all …]
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| /external/llvm-project/llvm/test/CodeGen/Thumb2/ |
| D | float-intrinsics-float.ll | 7 … | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=NEON-A57 -check-prefix=FP-AR…
133 ; NEON-A57: @ %bb.0:
134 ; NEON-A57-NEXT: vmov.f32 s2, s1
135 ; NEON-A57-NEXT: vmov.i32 d16, #0x80000000
136 ; NEON-A57-NEXT: @ kill: def $s0 killed $s0 def $d0
137 ; NEON-A57-NEXT: vbit d0, d1, d16
138 ; NEON-A57-NEXT: @ kill: def $s0 killed $s0 killed $d0
139 ; NEON-A57-NEXT: bx lr
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | arm64-scvt.ll | 2 …< %s -mtriple=arm64-eabi -mcpu=cortex-a57 | FileCheck -enable-var-scope --check-prefix=CHECK-A57 %s
413 ; CHECK-A57-LABEL: sfct1:
414 ; CHECK-A57: ldrsb w[[REGNUM:[0-9]+]], [x0, #1]
415 ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
416 ; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
474 ; CHECK-A57-LABEL: sfct5:
475 ; CHECK-A57: ldrsb w[[REGNUM:[0-9]+]], [x0, x1]
476 ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
477 ; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
548 ; CHECK-A57-LABEL: sfct10:
[all …]
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| D | arm64-misched-basic-A57.ll | 3 ; The Cortext-A57 machine model will avoid scheduling load instructions in
4 ; succession because loads on the A57 have a latency of 4 cycles and they all
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-scvt.ll | 2 ; RUN: llc < %s -march=arm64 -mcpu=cortex-a57 | FileCheck --check-prefix=CHECK-A57 %s
413 ; CHECK-A57-LABEL: sfct1:
414 ; CHECK-A57: ldrsb w[[REGNUM:[0-9]+]], [x0, #1]
415 ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
416 ; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
474 ; CHECK-A57-LABEL: sfct5:
475 ; CHECK-A57: ldrsb w[[REGNUM:[0-9]+]], [x0, x1]
476 ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
477 ; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
548 ; CHECK-A57-LABEL: sfct10:
[all …]
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| D | arm64-misched-basic-A57.ll | 3 ; The Cortext-A57 machine model will avoid scheduling load instructions in
4 ; succession because loads on the A57 have a latency of 4 cycles and they all
|
| /external/arm-trusted-firmware/docs/plat/ |
| D | nvidia-tegra.rst | 22 T186 has Dual NVIDIA Denver 2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores,
23 in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores
27 unified cache. The Cortex-A57 processors each have 48 KB Instruction and 32 KB
35 T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a
36 companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores
38 including legacy Armv7-A applications. The Cortex-A57 processors each have
151 Protection bit, for Arm Cortex-A57 CPUs, during CPU boot. This flag will
|
| /external/arm-trusted-firmware/plat/arm/board/juno/aarch32/ |
| D | juno_helpers.S | 97 jump_if_cpu_midr CORTEX_A57_MIDR, A57
100 A57: label
|
| /external/arm-trusted-firmware/plat/arm/board/juno/aarch64/ |
| D | juno_helpers.S | 101 jump_if_cpu_midr CORTEX_A57_MIDR, A57
104 A57: label
|
| /external/OpenCSD/decoder/tests/snapshots/init-short-addr/ |
| D | device1.ini | 4 type=Cortex-A57
|
| /external/OpenCSD/decoder/tests/snapshots/juno_r1_1/ |
| D | cpu_5.ini | 4 type=Cortex-A57
|
| D | cpu_4.ini | 4 type=Cortex-A57
|
| /external/OpenCSD/decoder/tests/snapshots/juno-ret-stck/ |
| D | cpu_4.ini | 4 type=Cortex-A57
|
| D | cpu_5.ini | 4 type=Cortex-A57
|
| /external/OpenCSD/decoder/tests/snapshots-ete/infrastructure/ |
| D | cpu_4.ini | 4 type=Cortex-A57
|
| D | cpu_5.ini | 4 type=Cortex-A57
|
| /external/llvm/test/CodeGen/ARM/ |
| D | build-attributes.ll | 120 …UN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57
121 …nfs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A57-FAST
1344 ; CORTEX-A57: .cpu cortex-a57
1345 ; CORTEX-A57: .eabi_attribute 6, 14
1346 ; CORTEX-A57: .eabi_attribute 7, 65
1347 ; CORTEX-A57: .eabi_attribute 8, 1
1348 ; CORTEX-A57: .eabi_attribute 9, 2
1349 ; CORTEX-A57: .fpu crypto-neon-fp-armv8
1350 ; CORTEX-A57: .eabi_attribute 12, 3
1351 ; CORTEX-A57-NOT: .eabi_attribute 19
[all …]
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| /external/arm-trusted-firmware/plat/renesas/common/aarch64/ |
| D | plat_helpers.S | 350 b.eq A57
352 A57: label
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | build-attributes.ll | 133 …UN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57
134 …nfs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A57-FAST
1486 ; CORTEX-A57: .cpu cortex-a57
1487 ; CORTEX-A57: .eabi_attribute 6, 14
1488 ; CORTEX-A57: .eabi_attribute 7, 65
1489 ; CORTEX-A57: .eabi_attribute 8, 1
1490 ; CORTEX-A57: .eabi_attribute 9, 2
1491 ; CORTEX-A57: .fpu crypto-neon-fp-armv8
1492 ; CORTEX-A57: .eabi_attribute 12, 3
1493 ; CORTEX-A57-NOT: .eabi_attribute 27
[all …]
|
| /external/arm-trusted-firmware/docs/security_advisories/ |
| D | security-advisory-tfv-6.rst | 47 For Cortex-A57 and Cortex-A72 CPUs, the Pull Requests (PRs) in this advisory
74 ``SMCCC_ARCH_WORKAROUND_1`` SMCs on Cortex-A57, using both the "MMU
80 at invalidating the branch predictor on Cortex-A57, the drop into Secure-EL1
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64.td | 173 "Cortex-A57 ARM processors", [
267 // FIXME: Cortex-A72 and Cortex-A73 are currently modelled as an Cortex-A57.
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleA57WriteRes.td | 1 //=- ARMScheduleA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=//
9 // Contains all of the Cortex-A57 specific SchedWriteRes types. The approach
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMScheduleA57WriteRes.td | 1 //=- ARMScheduleA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=//
9 // Contains all of the Cortex-A57 specific SchedWriteRes types. The approach
|
| /external/arm-trusted-firmware/docs/perf/ |
| D | psci-performance-juno.rst | 13 x Cortex-A57 clusters running at the following frequencies:
18 | Cortex-A57 | 900 (nominal) |
58 CPUs 4-5 refer to CPUs in the big cluster (A57). In all cases CPU 4 is the lead
|
| /external/rust/crates/ring/pregenerated/ |
| D | aesv8-armx-ios32.S | 261 @ ARM Cortex-A57 and Cortex-A72 cores running in 32-bit mode are
272 @ [0] ARM-EPM-049219 v23 Cortex-A57 MPCore Software Developers Errata Notice
342 @ around a bug in ARM Cortex-A57 and Cortex-A72 cores running in
|