1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef HI6220_H 8 #define HI6220_H 9 10 #include <hi6220_regs_acpu.h> 11 #include <hi6220_regs_ao.h> 12 #include <hi6220_regs_peri.h> 13 #include <hi6220_regs_pin.h> 14 #include <hi6220_regs_pmctrl.h> 15 16 /******************************************************************************* 17 * Implementation defined ACTLR_EL2 bit definitions 18 ******************************************************************************/ 19 #define ACTLR_EL2_L2ACTLR_BIT (1 << 6) 20 #define ACTLR_EL2_L2ECTLR_BIT (1 << 5) 21 #define ACTLR_EL2_L2CTLR_BIT (1 << 4) 22 #define ACTLR_EL2_CPUECTLR_BIT (1 << 1) 23 #define ACTLR_EL2_CPUACTLR_BIT (1 << 0) 24 25 /******************************************************************************* 26 * Implementation defined ACTLR_EL3 bit definitions 27 ******************************************************************************/ 28 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 29 #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 30 #define ACTLR_EL3_L2CTLR_BIT (1 << 4) 31 #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 32 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 33 34 /******************************************************************************* 35 * CCI-400 related constants 36 ******************************************************************************/ 37 #define CCI400_BASE 0xF6E90000 38 #define CCI400_SL_IFACE3_CLUSTER_IX 3 39 #define CCI400_SL_IFACE4_CLUSTER_IX 4 40 41 #define DWMMC0_BASE 0xF723D000 42 43 #define DWUSB_BASE 0xF72C0000 44 45 #define EDMAC_BASE 0xf7370000 46 #define EDMAC_SEC_CTRL (EDMAC_BASE + 0x694) 47 #define EDMAC_AXI_CONF(x) (EDMAC_BASE + 0x820 + (x << 6)) 48 #define EDMAC_SEC_CTRL_INTR_SEC (1 << 1) 49 #define EDMAC_SEC_CTRL_GLOBAL_SEC (1 << 0) 50 #define EDMAC_CHANNEL_NUMS 16 51 52 #define PMUSSI_BASE 0xF8000000 53 54 #define SP804_TIMER0_BASE 0xF8008000 55 56 #define GPIO0_BASE 0xF8011000 57 #define GPIO1_BASE 0xF8012000 58 #define GPIO2_BASE 0xF8013000 59 #define GPIO3_BASE 0xF8014000 60 #define GPIO4_BASE 0xF7020000 61 #define GPIO5_BASE 0xF7021000 62 #define GPIO6_BASE 0xF7022000 63 #define GPIO7_BASE 0xF7023000 64 #define GPIO8_BASE 0xF7024000 65 #define GPIO9_BASE 0xF7025000 66 #define GPIO10_BASE 0xF7026000 67 #define GPIO11_BASE 0xF7027000 68 #define GPIO12_BASE 0xF7028000 69 #define GPIO13_BASE 0xF7029000 70 #define GPIO14_BASE 0xF702A000 71 #define GPIO15_BASE 0xF702B000 72 #define GPIO16_BASE 0xF702C000 73 #define GPIO17_BASE 0xF702D000 74 #define GPIO18_BASE 0xF702E000 75 #define GPIO19_BASE 0xF702F000 76 77 #endif /* HI6220_H */ 78