| /external/llvm/test/CodeGen/ARM/ |
| D | copy-cpsr.ll | 6 ; escape. However, for long ADCS chains (and last ditch fallback) the dependency
12 ; + We want 2 long ADCS chains
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | copy-cpsr.ll | 6 ; escape. However, for long ADCS chains (and last ditch fallback) the dependency
12 ; + We want 2 long ADCS chains
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | nzcv-save.ll | 6 ; DAG ends up with two uses for the flags from an ADCS node, which means they
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | nzcv-save.ll | 6 ; DAG ends up with two uses for the flags from an ADCS node, which means they
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 487 ADCS r5, r2, r1 // Must be wide - 3 distinct registers
488 ADCS r5, r5, r1 // Should choose narrow
489 ADCS r3, r1, r3 // Should choose narrow - commutative
490 ADCS.W r2, r2, r1 // Explicitly wide
491 ADCS.W r3, r1, r3
493 ADCS r7, r7, r1 // Should use narrow
494 ADCS r7, r1, r7 // Commutative
495 ADCS r8, r1, r8 // high registers so must use wide encoding
496 ADCS r8, r8, r1
497 ADCS r5, r8, r5
[all …]
|
| /external/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 487 ADCS r5, r2, r1 // Must be wide - 3 distinct registers
488 ADCS r5, r5, r1 // Should choose narrow
489 ADCS r3, r1, r3 // Should choose narrow - commutative
490 ADCS.W r2, r2, r1 // Explicitly wide
491 ADCS.W r3, r1, r3
493 ADCS r7, r7, r1 // Should use narrow
494 ADCS r7, r1, r7 // Commutative
495 ADCS r8, r1, r8 // high registers so must use wide encoding
496 ADCS r8, r8, r1
497 ADCS r5, r8, r5
[all …]
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-operand-const-a32.json | 30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
|
| D | cond-rd-rn-operand-rm-t32.json | 48 "Adcs", // ADCS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
49 // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
|
| D | cond-rd-rn-operand-rm-shift-rs-a32.json | 30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
|
| D | cond-rd-rn-operand-const-t32.json | 37 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
|
| D | cond-rd-rn-operand-rm-shift-amount-1to31-a32.json | 30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| D | cond-rd-rn-operand-rm-shift-amount-1to32-a32.json | 30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| D | cond-rd-rn-operand-rm-shift-amount-1to32-t32.json | 34 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
|
| D | cond-rd-rn-operand-rm-shift-amount-1to31-t32.json | 34 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
|
| D | cond-rd-rn-operand-rm-a32.json | 39 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 58 ADCS, enumerator
|
| D | AArch64ISelLowering.cpp | 853 case AArch64ISD::ADCS: return "AArch64ISD::ADCS"; in getTargetNodeName()
1816 Opc = AArch64ISD::ADCS; in LowerADDC_ADDE_SUBC_SUBE()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 58 ADCS, enumerator
|
| D | AArch64ISelLowering.cpp | 1253 case AArch64ISD::ADCS: return "AArch64ISD::ADCS"; in getTargetNodeName()
2444 Opc = AArch64ISD::ADCS; in LowerADDC_ADDE_SUBC_SUBE()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 123 ADCS, enumerator
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_T2_32.c | 95 #define ADCS 0x4140 macro
811 return push_inst16(compiler, ADCS | RD3(dst) | RN3(arg2)); in emit_op_imm()
|
| /external/OpenCSD/decoder/tests/snapshots/TC2/ds5-dumps/ |
| D | etmv3_0x12.txt | 522 Instruction 506 S:0xC00430DA 0xEB5C0C05 1 ADCS r12,r12,r5 false
1318 Instruction 1285 S:0xC0034D8C 0x4158 1 ADCS r0,r0,r3 false
|
| D | ptmv1_0x13.txt | 1796 Instruction 1719 S:0xC0043F66 0xEB590900 0 ADCS r9,r9,r0 false
3506 Instruction 3393 S:0xC0035228 0x416B 0 ADCS r3,r3,r5 false
3932 Instruction 3811 S:0xC0034D8C 0x4158 0 ADCS r0,r0,r3 false
6021 Instruction 5805 S:0xC0043F66 0xEB590900 0 ADCS r9,r9,r0 false
7638 Instruction 7369 S:0xC0042430 0x4160 0 ADCS r0,r0,r4 false
9119 Instruction 8818 S:0xC004275A 0x414D 0 ADCS r5,r5,r1 false
9737 Instruction 9421 S:0xC0041F76 0x417E 0 ADCS r6,r6,r7 false
|
| D | etmv3_0x10.txt | 1696 Instruction 1574 S:0xC004275A 0x414D 1 ADCS r5,r5,r1 false
2505 Instruction 2366 S:0xC0041F76 0x417E 1 ADCS r6,r6,r7 false
3970 Instruction 3776 S:0xC00430DA 0xEB5C0C05 1 ADCS r12,r12,r5 false
4823 Instruction 4608 S:0xC0034D8C 0x4158 1 ADCS r0,r0,r3 false
6974 Instruction 6666 S:0xC0043F66 0xEB590900 1 ADCS r9,r9,r0 false
|
| D | etmv3_0x11.txt | 1089 Instruction 1059 S:0xC0043F66 0xEB590900 1 ADCS r9,r9,r0 false
2358 Instruction 2309 S:0xC00430DA 0xEB5C0C05 1 ADCS r12,r12,r5 false
3156 Instruction 3088 S:0xC0034D8C 0x4158 1 ADCS r0,r0,r3 false
6558 Instruction 6341 S:0xC004275A 0x414D 1 ADCS r5,r5,r1 false
7143 Instruction 6914 S:0xC0041F76 0x417E 1 ADCS r6,r6,r7 false
|