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/external/mesa3d/src/gallium/drivers/nouveau/nvc0/mme/
Dcomc597.mme.h117 MME_INSN(0, ADD, R1, LOAD0, ZERO, (1<<12)|0x1880/4, IMMED0, NONE,
118 ADD, R3, LOAD1, ZERO, 0, NONE, NONE),
124 ADD, ZERO, ZERO, ZERO, 0, NONE, NONE),
126 ADD, ZERO, ZERO, ZERO, 0, NONE, NONE),
128 ADD, ZERO, ZERO, ZERO, 0, NONE, NONE),
129 MME_INSN(1, ADD, ZERO, ZERO, ZERO, 0, NONE, NONE,
130 ADD, ZERO, ZERO, ZERO, 0, NONE, NONE),
131 MME_INSN(0, ADD, ZERO, ZERO, ZERO, 0, NONE, NONE,
132 ADD, ZERO, ZERO, ZERO, 0, NONE, NONE),
149 MME_INSN(0, ADD, R1, LOAD0, ZERO, 0, NONE, NONE,
[all …]
/external/libxaac/decoder/armv7/
Dixheaacd_fft_15_ld.s18 ADD r0, r0, r12
20 ADD r0, r0, r12
22 ADD r0, r0, r12
24 ADD r0, r0, r12
28 ADD r1, r4, r10 @ r1 = buf1a[2] + buf1a[8]
32 ADD r12, r6, r8 @ r3 = buf1a[4] + buf1a[6]
37 ADD r1, r1, r12 @ r1 = r1 + r3@
38 ADD r2, r2, r1 @ temp1 = inp[0] + r1@
40 ADD r1, r2, r1, lsl #2 @ r1 = temp1 + ((mult32_shl(r1, C55)) << 1)@
46 ADD r1, r1, r6, LSL #1 @ r1 = r1 + t@
[all …]
Dixheaacd_post_radix_compute4.s43 ADD r4, r1, r3, lsl #1
51 ADD r14, r5, r9
54 ADD r9, r6, r10
57 ADD r10, r7, r11
60 ADD r11, r8, r12
63 ADD r12, r14, r10
66 ADD r10, r9, r11
69 ADD r11, r5, r8
72 ADD r8, r6, r7
92 ADD r14, r5, r9
[all …]
Dixheaacd_sbr_qmfanal32_winadds.s37 ADD r5, r5, #64
79 ADD R0, R0, #120
83 ADD R11, R11, #128
89 ADD R2, R2, #240
93 ADD R2, R2, #240
102 ADD R2, R2, #240
109 ADD R2, R2, #240
117 ADD R2, R2, #240
125 ADD R1, R1, #120
132 ADD R3, R3, #240
[all …]
Dixheaacd_post_radix_compute2.s48 ADD r4, r1, r3, lsl #1
59 ADD r0, r0, r14
61 ADD r14, r5, r7
64 ADD r7, r9, r11
67 ADD r11, r6, r8
70 ADD r8, r10, r12
91 ADD r0, r0, r14
94 ADD r0, r0, #8
96 ADD r14, r5, r7
99 ADD r7, r9, r11
[all …]
Dixheaacd_fft32x32_ld2_armv7.s17 ADD r6, r2, r4 @xh0_0 = x_0 + x_4
19 ADD r8, r3, r5 @xh0_1 = x_2 + x_6
26 ADD r10, r2, r4 @xh1_0 = x_1 + x_5
28 ADD r12, r3, r5 @xh1_1 = x_3 + x_7
31 ADD r2, r6, r8 @n00 = xh0_0 + xh0_1
32 ADD r3, r7, r14 @n10 = xl0_0 + xl1_1
40 ADD r2, r10, r12 @n01 = xh1_0 + xh1_1
43 ADD r5, r11, r9 @n31 = xl1_0 + xl0_1
54 ADD r6, r2, r4 @xh0_0 = x_0 + x_4
56 ADD r8, r3, r5 @xh0_1 = x_2 + x_6
[all …]
Dixheaacd_mps_complex_fft_64_asm.s29 ADD r1, r2, r10, LSL #2
31 ADD r1, r1, lr
33 ADD r1, r1, lr
35 ADD r1, r1, lr
37 ADD r0, r0, #4
40 ADD r4, r4, r6 @x0r = x0r + x2r@
41 ADD r5, r5, r7 @x0i = x0i + x2i@
44 ADD r8, r8, r10 @x1r = x1r + x3r@
45 ADD r9, r9, r11 @x1i = x1i + x3i@
49 ADD r4, r4, r8 @x0r = x0r + x1r@
[all …]
Dixheaacd_complex_ifft_p2.s44 ADD r1, r2, r10, LSL #2
46 ADD r1, r1, lr
48 ADD r1, r1, lr
50 ADD r1, r1, lr
52 ADD r0, r0, #4
55 ADD r4, r4, r6 @x0r = x0r + x2r@
56 ADD r5, r5, r7 @x0i = x0i + x2i@
59 ADD r8, r8, r10 @x1r = x1r + x3r@
60 ADD r9, r9, r11 @x1i = x1i + x3i@
64 ADD r4, r4, r8 @x0r = x0r + x1r@
[all …]
Dixheaacd_complex_fft_p2.s44 ADD r1, r2, r10, LSL #2
46 ADD r1, r1, lr
48 ADD r1, r1, lr
50 ADD r1, r1, lr
52 ADD r0, r0, #4
55 ADD r4, r4, r6 @x0r = x0r + x2r@
56 ADD r5, r5, r7 @x0i = x0i + x2i@
59 ADD r8, r8, r10 @x1r = x1r + x3r@
60 ADD r9, r9, r11 @x1i = x1i + x3i@
64 ADD r4, r4, r8 @x0r = x0r + x1r@
[all …]
Dixheaacd_sbr_qmfanal32_winadds_eld.s16 ADD r5, r5, #64
59 ADD R0, R0, #120 @ incrementing R0 by 120 + 8 = 128
63 ADD R11, R11, #128 @ increment winAdd by 128
67 ADD R2, R2, #112 @ This should be 240 --> 112
71 ADD R2, R2, #112 @ This should be 112
81 ADD R2, R2, #112 @ This should be 112
88 ADD R2, R2, #112 @ This should be 112
96 ADD R2, R2, #112 @ This should be 112
104 ADD R1, R1, #120 @ incrementing R1 by 120 + 8 = 128
111 ADD R3, R3, #112 @ This sholud be 112
[all …]
Dixheaacd_decorr_filter2.s48 ADD r11, r9, #0x0150
50 ADD r2, r2, #12
51 ADD r10, r10, #12
53 ADD r5, r5, #140
55 ADD r6, r6, #268
61 ADD r11, r11, #0x0c
64 ADD r2, r9, #0x012
65 ADD r12, r11, #0x0a0
69 ADD r3, r3, #12
78 ADD r1, r1, #12
[all …]
/external/libxaac/decoder/armv8/
Dixheaacd_fft32x32_ld2_armv8.s48 ADD w6, w2, w4 //xh0_0 = x_0 + x_4
50 ADD w8, w3, w5 //xh0_1 = x_2 + x_6
61 ADD w10, w2, w4 //xh1_0 = x_1 + x_5
63 ADD w12, w3, w5 //xh1_1 = x_3 + x_7
66 ADD w2, w6, w8 //n00 = xh0_0 + xh0_1
67 ADD w3, w7, w14 //n10 = xl0_0 + xl1_1
75 ADD w2, w10, w12 //n01 = xh1_0 + xh1_1
78 ADD w5, w11, w9 //n31 = xl1_0 + xl0_1
93 ADD w6, w2, w4 //xh0_0 = x_0 + x_4
95 ADD w8, w3, w5 //xh0_1 = x_2 + x_6
[all …]
Dixheaacd_sbr_qmf_analysis32_neon.s47 ADD x5, x5, #64
59 ADD x6, x6, x9
61 ADD x6, x6, x9
63 ADD x6, x6, x9
65 ADD x6, x6, x9
73 ADD x6, x6, x9
75 ADD x6, x6, x9
77 ADD x6, x6, x9
79 ADD x6, x6, x9
151 ADD x0, x0, #120
[all …]
Dixheaacd_postradixcompute4.s38 ADD x4, x1, x3, lsl #1 // x1 -> x0, x4 -> x2
51 ADD w14, w5, w9 // xh0_0 = x_0 + x_4
54 ADD w9, w6, w10 // xh1_0 = x_1 + x_5
57 ADD w10, w7, w11 // xh0_1 = x_2 + x_6
60 ADD w11, w8, w12 // xh1_1 = x_3 + x_7
63 ADD w12, w14, w10 // n00 = xh0_0 + xh0_1
66 ADD w10, w9, w11 // n01 = xh1_0 + xh1_1
69 ADD w11, w5, w8 // n10 = xl0_0 + xl1_1
72 ADD w8, w6, w7 // n31 = xl1_0 + xl0_1
99 ADD w14, w5, w9
[all …]
Dixheaacd_cos_sin_mod_loop1.s42 ADD x4, x0, x1, lsl #3 //psubband1
44 ADD x5, x3, x1, lsl #3 //psubband1_t
53 ADD x2, x2, #2
55 ADD x2, x2, #2
58 ADD x0, x0, #4
59 ADD x7, x0, #252
62 ADD x7, x4, #256
83 ADD x3, x3, #8
84 ADD x7, x3, #248
90 ADD x2, x2, #2
[all …]
Dixheaacd_sbr_imdct_using_fft.s105 ADD X5, X5, X12, LSL #3
107 ADD X5, X5, X1
111 ADD X5, X5, X1
116 ADD X6, X6, X12, LSL #3
118 ADD X6, X6, X1
122 ADD X6, X6, X1
128 ADD X7, X7, X12, LSL #3
130 ADD X7, X7, X1
135 ADD X11, X11, X12, LSL #3
137 ADD X11, X11, X1
[all …]
Dixheaacd_imdct_using_fft.s59 ADD X4, X0, X29
61 ADD X5, X0, X29
63 ADD X6, X0, X29
65 ADD X7, X0, X29
135 ADD X5, X5, X12, LSL #3
137 ADD X5, X5, X1
141 ADD X5, X5, X1
146 ADD X6, X6, X12, LSL #3
148 ADD X6, X6, X1
152 ADD X6, X6, X1
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dexecute-only-big-stack-frame.ll4 ; RUN: | FileCheck --check-prefix=CHECK-MOVW-MOVT-ADD %s
6 ; RUN: | FileCheck --check-prefix=CHECK-MOVW-MOVT-ADD %s
22 ; CHECK-MOVW-MOVT-ADD-LABEL: test_big_stack_frame:
23 ; CHECK-MOVW-MOVT-ADD-NOT: ldr {{r[0-9]+}}, .{{.*}}
24 ; CHECK-MOVW-MOVT-ADD: movw [[REG1:r[0-9]+]], #0
25 ; CHECK-MOVW-MOVT-ADD: movt [[REG1]], #65535
26 ; CHECK-MOVW-MOVT-ADD: add sp, [[REG1]]
27 ; CHECK-MOVW-MOVT-ADD-NOT: ldr {{r[0-9]+}}, .{{.*}}
28 ; CHECK-MOVW-MOVT-ADD: movw [[REG2:r[0-9]+]], #65532
29 ; CHECK-MOVW-MOVT-ADD: movt [[REG2]], #0
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dslow-incdec.ll3 …386-unknown-linux-gnu -mattr=+slow-incdec < %s | FileCheck -check-prefix=CHECK -check-prefix=ADD %s
12 ; ADD-LABEL: inc:
13 ; ADD: # %bb.0:
14 ; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
15 ; ADD-NEXT: addl $1, %eax
16 ; ADD-NEXT: retl
28 ; ADD-LABEL: dec:
29 ; ADD: # %bb.0:
30 ; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
31 ; ADD-NEXT: addl $-1, %eax
[all …]
/external/llvm-project/llvm/test/tools/llvm-objcopy/COFF/
Dadd-section.test7 …llvm-readobj --file-headers --sections --section-data %t1 | FileCheck %s --check-prefixes=CHECK-ADD
9 # CHECK-ADD: SectionCount: 2
10 # CHECK-ADD: Name: .text
11 # CHECK-ADD: Name: .test.section
12 # CHECK-ADD: Characteristics [
13 # CHECK-ADD-NEXT: IMAGE_SCN_ALIGN_1BYTES
14 # CHECK-ADD-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA
15 # CHECK-ADD-NEXT: ]
16 # CHECK-ADD: SectionData (
17 # CHECK-ADD-NEXT: 0000: {{.+}}|DEADBEEF{{.+}}|
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dfadd.ll6 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
15 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
16 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
26 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
27 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
28 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
29 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
44 ; R600: ADD
45 ; R600: ADD
46 ; R600: ADD
[all …]
/external/python/cpython2/PC/VC6/
Dw9xpopen.dsp45 # ADD BASE CPP /nologo /W3 /GX /O2 /D "Py_BUILD_CORE_MODULE" /D "WIN32" /D "NDEBUG" /D "_WINDOWS" /…
46 # ADD CPP /nologo /MD /W3 /GX /O2 /D "Py_BUILD_CORE_MODULE" /D "WIN32" /D "NDEBUG" /D "_WINDOWS" /D…
47 # ADD BASE MTL /nologo /D "NDEBUG" /mktyplib203 /win32
48 # ADD MTL /nologo /D "NDEBUG" /mktyplib203 /win32
49 # ADD BASE RSC /l 0xc09 /d "NDEBUG"
50 # ADD RSC /l 0xc09 /d "NDEBUG"
52 # ADD BASE BSC32 /nologo
53 # ADD BSC32 /nologo
55 # ADD BASE LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.…
56 # ADD LINK32 user32.lib /nologo /machine:I386
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dfadd.ll6 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
15 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
16 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
26 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
27 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
28 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
29 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
44 ; R600: ADD
45 ; R600: ADD
46 ; R600: ADD
[all …]
/external/freetype/builds/windows/visualce/
Dfreetype.dsp47 # ADD BASE CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_MBCS" /D "_LIB" /YX /FD /c
48 # ADD CPP /MD /Za /W4 /GX /O2 /I "..\..\..\include" /D "NDEBUG" /D "WIN32" /D "_MBCS" /D "_LIB" /D …
50 # ADD BASE RSC /l 0x409 /d "NDEBUG"
51 # ADD RSC /l 0x409 /d "NDEBUG"
53 # ADD BASE BSC32 /nologo
54 # ADD BSC32 /nologo
56 # ADD BASE LIB32 /nologo
57 # ADD LIB32 /nologo /out:"..\..\..\objs\freetype.lib"
71 # ADD BASE CPP /nologo /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_MBCS" /D "_LIB" /YX /FD /GZ …
72 # ADD CPP /MDd /Za /W4 /GX /Z7 /Od /I "..\..\..\include" /D "_DEBUG" /D "FT_DEBUG_LEVEL_ERROR" /D "…
[all …]
/external/libhevc/common/arm64/
Dihevc_sao_edge_offset_class3.s105 ADD x12,sp,#0x02 //temp array
126 ADD x11,x0,x1 //pu1_src + src_strd
143 …ADD x11,x12,x11 //SIGN(pu1_src[wd - 1] - pu1_src_top_right[0]) + SIGN(pu1…
144 ADD x11,x11,#2 //edge_idx
150 ADD x9,x9,x10 //pu1_src[0] + pi1_sao_offset[edge_idx]
172 ADD x11,x11,#1 //pu1_src[(ht - 1) * src_strd + 1 - src_strd]
190 ADD x11,x11,x14 //Add 2 sign value
194 ADD x11,x11,#2 //edge_idx
200 … ADD x10,x10,x11 //pu1_src[(ht - 1) * src_strd] + pi1_sao_offset[edge_idx]
225 ADD x20,x0,x1 //pu1_src += src_strd
[all …]

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