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Searched refs:ADD2 (Results 1 – 25 of 96) sorted by relevance

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/external/llvm-project/llvm/test/Transforms/InstCombine/
Dreassociate-nuw.ll59 ; CHECK-NEXT: [[ADD2:%.*]] = add nuw i32 [[ADD1]], 12
60 ; CHECK-NEXT: ret i32 [[ADD2]]
95 ; CHECK-NEXT: [[ADD2:%.*]] = shl nuw i32 [[X:%.*]], 2
96 ; CHECK-NEXT: ret i32 [[ADD2]]
105 ; CHECK-NEXT: [[ADD2:%.*]] = shl nuw i32 [[X:%.*]], 31
106 ; CHECK-NEXT: ret i32 [[ADD2]]
115 ; CHECK-NEXT: [[ADD2:%.*]] = shl i32 [[X:%.*]], 2
116 ; CHECK-NEXT: ret i32 [[ADD2]]
125 ; CHECK-NEXT: [[ADD2:%.*]] = shl i32 [[X:%.*]], 2
126 ; CHECK-NEXT: ret i32 [[ADD2]]
Dadd2.ll219 ; CHECK-NEXT: [[ADD2:%.*]] = mul nsw i16 [[X:%.*]], 3
220 ; CHECK-NEXT: ret i16 [[ADD2]]
229 ; CHECK-NEXT: [[ADD2:%.*]] = mul nsw i16 [[X:%.*]], 9
230 ; CHECK-NEXT: ret i16 [[ADD2]]
239 ; CHECK-NEXT: [[ADD2:%.*]] = mul nsw i16 [[X:%.*]], 9
240 ; CHECK-NEXT: ret i16 [[ADD2]]
294 ; CHECK-NEXT: [[ADD2:%.*]] = shl i16 [[X:%.*]], 15
295 ; CHECK-NEXT: ret i16 [[ADD2]]
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
Dbreakup-islands.mlir25 // CHECK: %[[ADD2:.*]], %[[ADD2_control:.*]] = tf_executor.island wraps "tf.Add"(%[[ADD1]], %ar…
26 // CHECK: tf_executor.fetch %[[ADD1]], %[[ADD2]] :
61 // CHECK: %[[ADD2:.*]], %[[ADD2_control:.*]] = tf_executor.island wraps "tf.Add"(%[[ADD1]], %arg…
67 …rol:.*]] = tf_executor.island(%[[ISLAND1]], %[[ADD2_control]]) wraps "tf.Add"(%[[ADD2]], %[[ADD2]])
69 // CHECK: tf_executor.fetch %[[ADD2]], %[[MUL]], %[[PRINT1_control]], %[[PRINT2_control:.*]] :
89 // CHECK: %[[ADD2:.*]], %[[ADD2_control:.*]] = tf_executor.island wraps "tf.Add"(%[[ADD1_control…
91 // CHECK: tf_executor.fetch %[[ADD1]], %[[ADD2]], %[[PRINT_control]] :
122 // CHECK: %[[ADD2:.*]], %[[ADD2_control:.*]] = tf_executor.island wraps "tf.Add"(%[[SWITCH_false]…
123 // CHECK: %[[PRINT2:.*]], %[[PRINT2_control:.*]] = tf_executor.island wraps "tf.Print"(%[[ADD2]])…
124 // CHECK: %[[MERGE:.*]], %[[MERGE_index:.*]], %{{.*}} = tf_executor.Merge %[[ADD2]], %[[SWITCH_tr…
[all …]
Dtf-functional-to-executor.mlir14 // CHECK: %[[ADD2:.*]] = "tf.Add"(%[[ADD1]], %[[ARG1]]) : (tensor<*xi32>, tensor<i32>) -> te…
15 // CHECK: tf_executor.yield %[[ADD1]], %[[ADD2]] : tensor<*xi32>, tensor<*xi32>
Dpromote_resources_to_args.mlir41 // CHECK: %[[ADD2:[0-9]*]] = "tf.AddV2"(%[[ADD1]], %arg1)
42 // CHECK: %[[PACK:[0-9]*]] = "tf.Pack"(%[[CONST]], %[[ADD2]])
64 // CHECK: %[[ADD2:[0-9]*]] = "tf.AddV2"(%[[ADD1]], %arg2)
65 // CHECK: %[[PACK:[0-9]*]] = "tf.Pack"(%[[CONST]], %[[ADD2]])
86 // CHECK: %[[ADD2:[0-9]*]] = "tf.AddV2"(%[[ADD1]], %[[ADD1]])
87 // CHECK: %[[PACK:[0-9]*]] = "tf.Pack"(%arg1, %[[ADD2]])
110 // CHECK: %[[ADD2:[0-9]*]] = "tf.AddV2"(%[[ADD1]], %[[ADD1]])
111 // CHECK: %[[PACK:[0-9]*]] = "tf.Pack"(%[[CONST]], %[[ADD2]])
/external/llvm-project/llvm/test/CodeGen/X86/GlobalISel/
Dlegalize-add-v512.mir51 ; AVX1: [[ADD2:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV2]], [[UV6]]
53 …(<64 x s8>) = G_CONCAT_VECTORS [[ADD]](<16 x s8>), [[ADD1]](<16 x s8>), [[ADD2]](<16 x s8>), [[ADD…
98 ; AVX1: [[ADD2:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV2]], [[UV6]]
100 …<32 x s16>) = G_CONCAT_VECTORS [[ADD]](<8 x s16>), [[ADD1]](<8 x s16>), [[ADD2]](<8 x s16>), [[ADD…
145 ; AVX1: [[ADD2:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV2]], [[UV6]]
147 …<16 x s32>) = G_CONCAT_VECTORS [[ADD]](<4 x s32>), [[ADD1]](<4 x s32>), [[ADD2]](<4 x s32>), [[ADD…
188 ; AVX1: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV2]], [[UV6]]
190 …(<8 x s64>) = G_CONCAT_VECTORS [[ADD]](<2 x s64>), [[ADD1]](<2 x s64>), [[ADD2]](<2 x s64>), [[ADD…
243 ; AVX1: [[ADD2:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV2]], [[UV6]]
246 …; AVX1: [[CONCAT_VECTORS1:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[ADD2]](<16 x s8>), [[ADD3]](…
/external/libvpx/libvpx/vpx_dsp/mips/
Dfwd_dct32x32_msa.c90 ADD2(vec4, vec5, vec7, vec6, vec0, vec1); in fdct8x32_1d_column_even_store()
106 ADD2(in0, in1, in2, in3, vec0, vec7); in fdct8x32_1d_column_even_store()
126 ADD2(in3, in2, in0, in1, vec3, vec4); in fdct8x32_1d_column_even_store()
187 ADD2(in27, in26, in25, in24, in23, in20); in fdct8x32_1d_column_odd_store()
207 ADD2(in26, in27, in24, in25, in22, in21); in fdct8x32_1d_column_odd_store()
221 ADD2(in28, in29, in31, in30, in16, in19); in fdct8x32_1d_column_odd_store()
240 ADD2(in29, in28, in30, in31, in17, in18); in fdct8x32_1d_column_odd_store()
348 ADD2(vec4, vec5, vec7, vec6, vec0, vec1); in fdct8x32_1d_row_even_4x()
365 ADD2(in0, in1, in2, in3, vec0, vec7); in fdct8x32_1d_row_even_4x()
385 ADD2(in3, in2, in0, in1, vec3, vec4); in fdct8x32_1d_row_even_4x()
[all …]
Didct16x16_msa.c389 ADD2(res0, out0, res1, out1, res0, res1); in vpx_iadst16_1d_columns_addblk_msa()
406 ADD2(res8, out8, res9, out9, res8, res9); in vpx_iadst16_1d_columns_addblk_msa()
421 ADD2(res4, out4, res5, out5, res4, res5); in vpx_iadst16_1d_columns_addblk_msa()
433 ADD2(res12, out12, res13, out13, res12, res13); in vpx_iadst16_1d_columns_addblk_msa()
446 ADD2(res6, out6, res7, out7, res6, res7); in vpx_iadst16_1d_columns_addblk_msa()
457 ADD2(res10, out10, res11, out11, res10, res11); in vpx_iadst16_1d_columns_addblk_msa()
470 ADD2(res2, out2, res3, out3, res2, res3); in vpx_iadst16_1d_columns_addblk_msa()
481 ADD2(res14, out14, res15, out15, res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dmachine-cse-mid-pipeline.mir195 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]]
196 ; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)
229 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]]
230 ; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)
262 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]]
263 ; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)
290 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD0]], [[ADD1]]
291 ; CHECK-NEXT: $w0 = COPY [[ADD2]](s32)
Dprelegalizercombiner-br.mir59 ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = nuw nsw G_ADD [[MUL]], [[C1]]
61 ; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.1, [[ADD2]](s32), %bb.2
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
Dcrash_binaryop.ll15 ; CHECK-NEXT: [[PHI:%.*]] = phi double [ [[ADD2:%.*]], [[LOOP]] ], [ [[INIT]], [[ENTRY:%.*]] ]
19 ; CHECK-NEXT: [[ADD2]] = fadd double [[POSTADD2_PHI]], [[PHI]]
20 ; CHECK-NEXT: [[MUL2:%.*]] = fmul double [[ADD2]], 0.000000e+00
DPR36280.ll13 ; CHECK-NEXT: [[ADD2:%.*]] = fadd float [[MUL2]], [[ADD1]]
14 ; CHECK-NEXT: ret float [[ADD2]]
Dpr16899.ll18 ; CHECK-NEXT: [[C_0:%.*]] = phi i32 [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ADD2:%.*]], [[DO_BODY]] ]
21 ; CHECK-NEXT: [[ADD2]] = add nsw i32 [[ADD]], 1
Dcrash_reordering_undefs.ll12 ; CHECK-NEXT: [[ADD2:%.*]] = select i1 [[CMP1]], i32 65536, i32 65537
13 ; CHECK-NEXT: [[ADD3:%.*]] = add i32 [[ADD1]], [[ADD2]]
/external/llvm-project/llvm/test/Transforms/CallSiteSplitting/
Dsplit-loop.ll40 ; CHECK-NEXT: [[ADD2:%.*]] = add i16 [[S]], 10
69 ; CHECK-NEXT: [[ADD2:%.*]] = add i16 [[ADD]], 10
72 ; CHECK-NEXT: ret i16 [[ADD2]]
/external/llvm-project/clang/test/utils/update_cc_test_checks/Inputs/
Dmangled_names.c.expected36 // CHECK-NEXT: [[ADD2:%.*]] = add nsw i64 [[ADD]], [[CONV1]]
37 // CHECK-NEXT: ret i64 [[ADD2]]
Dmangled_names.c.funcsig.expected38 // CHECK-NEXT: [[ADD2:%.*]] = add nsw i64 [[ADD]], [[CONV1]]
39 // CHECK-NEXT: ret i64 [[ADD2]]
/external/llvm-project/llvm/test/Transforms/Reassociate/
Dmixed-fast-nonfast-fp.ll30 ; CHECK-NEXT: [[ADD2:%.*]] = fadd reassoc float [[MUL2]], [[MUL4]]
31 ; CHECK-NEXT: [[ADD3:%.*]] = fadd fast float [[ADD1]], [[ADD2]]
/external/libvpx/libvpx/vp8/encoder/mips/msa/
Ddenoising_msa.c111 ADD2(col_sum0, adjust0, col_sum1, adjust1, col_sum0, col_sum1); in vp8_denoiser_filter_msa()
113 ADD2(temp0_h, adjust0, temp1_h, adjust1, temp0_h, temp1_h); in vp8_denoiser_filter_msa()
159 ADD2(col_sum0, adjust0, col_sum1, adjust1, col_sum0, col_sum1); in vp8_denoiser_filter_msa()
161 ADD2(temp0_h, adjust0, temp1_h, adjust1, temp0_h, temp1_h); in vp8_denoiser_filter_msa()
224 ADD2(temp2_h, adjust0, temp3_h, adjust1, adjust2, adjust3); in vp8_denoiser_filter_msa()
237 ADD2(col_sum2, adjust0, col_sum3, adjust1, col_sum2, col_sum3); in vp8_denoiser_filter_msa()
258 ADD2(temp2_h, adjust0, temp3_h, adjust1, adjust2, adjust3); in vp8_denoiser_filter_msa()
271 ADD2(col_sum2, adjust0, col_sum3, adjust1, col_sum2, col_sum3); in vp8_denoiser_filter_msa()
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
Dctpop.mir80 ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[AND6]]
81 ; MIPS32: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD2]], [[C4]](s32)
82 ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD2]]
Dcttz.mir52 ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
53 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD2]]
136 ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
137 ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD2]]
/external/llvm-project/llvm/test/Transforms/SimplifyCFG/
Dmultiple-phis.ll25 ; CHECK-NEXT: [[ADD2:%.*]] = add i32 [[DIV]], 1
27 ; CHECK-NEXT: [[LOW_0_ADD2]] = select i1 [[CMP1]], i32 [[LOW_0]], i32 [[ADD2]]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-fptrunc.mir237 ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[C2]]
248 ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ADD2]], [[C9]](s32)
250 ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[ADD2]]
259 ; CHECK: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ADD2]](s32), [[C10]]
269 ; CHECK: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[ADD2]](s32), [[C17]]
271 ; CHECK: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[ADD2]](s32), [[C18]]
444 ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[C2]]
455 ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ADD2]], [[C9]](s32)
457 ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[ADD2]]
466 ; CHECK: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ADD2]](s32), [[C10]]
[all …]
/external/libaom/libaom/av1/encoder/mips/msa/
Dtemporal_filter_msa.c78 ADD2(mod0_h, cnt0, mod1_h, cnt1, mod0_h, mod1_h); in temporal_filter_apply_8size_msa()
125 ADD2(mod0_h, cnt0, mod1_h, cnt1, mod0_h, mod1_h); in temporal_filter_apply_8size_msa()
202 ADD2(mod0_h, cnt0, mod1_h, cnt1, mod0_h, mod1_h); in temporal_filter_apply_16size_msa()
249 ADD2(mod0_h, cnt0, mod1_h, cnt1, mod0_h, mod1_h); in temporal_filter_apply_16size_msa()
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dreassoc-scalar.ll50 ; GCN: s_add_i32 [[ADD2:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
52 ; GFX8: v_add_u32_e32 v{{[0-9]+}}, vcc, [[ADD2]], v{{[0-9]+}}
54 ; GFX9: v_add_u32_e32 v{{[0-9]+}}, [[ADD2]], v{{[0-9]+}}

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