| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 24 ADDC = 0x01, enumerator
80 case ADDC: in lanaiAluCodeToString()
106 .Case("addc", ADDC) in stringToLanaiAluCode()
123 return AluCode::ADDC; in isdToLanaiAluCode()
|
| /external/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 24 ADDC = 0x01, enumerator
80 case ADDC: in lanaiAluCodeToString()
106 .Case("addc", ADDC) in stringToLanaiAluCode()
123 return AluCode::ADDC; in isdToLanaiAluCode()
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 25 ADDC = 0x01, enumerator
81 case ADDC: in lanaiAluCodeToString()
107 .Case("addc", ADDC) in stringToLanaiAluCode()
124 return AluCode::ADDC; in isdToLanaiAluCode()
|
| /external/llvm-project/llvm/test/CodeGen/RISCV/ |
| D | addc-adde-sube-subc.ll | 5 ; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
|
| /external/llvm-project/llvm/test/CodeGen/Thumb/ |
| D | long.ll | 100 define i64 @f9a(i64 %x, i64 %y) { ; ADDC with small negative imm => SUBS imm
112 define i64 @f9b(i64 %x, i64 %y) { ; ADDC with big negative imm => SUBS reg
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 214 ADDC, SUBC, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 224 ADDC, SUBC, enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 262 ADDC, enumerator
|
| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/mme/ |
| D | comc597.mme.h | 781 ADDC, ZERO, R7, ZERO, (1<<12)|0x1b00/4, NONE, ALU0),
864 ADDC, R4, R4, R2, 0, NONE, ALU1),
885 ADDC, R2, R2, R4, 0, NONE, NONE),
899 ADDC, ZERO, R3, ZERO, (1<<12)|0x1b00/4, NONE, ALU0),
|
| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | aix-cc-byval-split.ll | 48 ; CHECK32: renamable $r4 = ADDC killed renamable $r8, killed renamable $r[[REG1]], implicit-def…
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 199 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in trySelect()
|
| /external/mesa3d/src/intel/compiler/ |
| D | brw_vec4.h | 221 EMIT2(ADDC)
|
| D | brw_vec4_builder.h | 397 ALU2_ACC(ADDC) in ALU2_ACC() argument
|
| D | brw_fs_builder.h | 559 ALU2_ACC(ADDC) in ALU2_ACC() argument
|
| /external/igt-gpu-tools/assembler/ |
| D | lex.l | 122 "addc" { yylval.integer = BRW_OPCODE_ADDC; return ADDC; }
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativePPC_32.c | 125 return push_inst(compiler, ADDC | RC(ALT_SET_FLAGS) | D(dst) | A(src1) | B(src2)); in emit_single_op()
|
| D | sljitNativeSPARC_32.c | 99 …return push_inst(compiler, ADDC | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(… in emit_single_op()
|
| D | sljitNativePPC_64.c | 259 return push_inst(compiler, ADDC | RC(ALT_SET_FLAGS) | D(dst) | A(src1) | B(src2)); in emit_single_op()
|
| /external/mesa3d/src/intel/tools/ |
| D | i965_lex.l | 53 addc { yylval.integer = BRW_OPCODE_ADDC; return ADDC; }
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 71 ADDC, // Add with carry enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 38 ADDC, // Add with carry: (X, Y, Cin) -> (X+Y, Cout). enumerator
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 39 ADDC, // Add with carry: (X, Y, Cin) -> (X+Y, Cout). enumerator
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 226 case ISD::ADDC: return "addc"; in getOperationName()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 90 setOperationAction(ISD::ADDC, MVT::i64, Expand); in BPFTargetLowering()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 104 ADDC, // Add with carry enumerator
|