Searched refs:ADDR_TM_1D_TILED_THIN1 (Results 1 – 6 of 6) sorted by relevance
754 localIn.tileMode = ADDR_TM_1D_TILED_THIN1; in HwlComputeSurfaceInfo()1061 tileMode = ADDR_TM_1D_TILED_THIN1; in HwlOverrideTileMode()1374 case ADDR_TM_1D_TILED_THIN1: in HwlSetupTileInfo()1390 case ADDR_TM_1D_TILED_THIN1: in HwlSetupTileInfo()1409 case ADDR_TM_1D_TILED_THIN1: in HwlSetupTileInfo()1461 case ADDR_TM_1D_TILED_THIN1: in HwlSetupTileInfo()
177 case ADDR_TM_1D_TILED_THIN1://fall through in DispatchComputeSurfaceInfo()616 return ComputeSurfaceInfoMicroTiled(pIn, pOut, padDims, ADDR_TM_1D_TILED_THIN1); in ComputeSurfaceInfoMacroTiled()1140 expTileMode = ADDR_TM_1D_TILED_THIN1; in ComputeSurfaceMipLevelTileMode()1249 expTileMode = ADDR_TM_1D_TILED_THIN1; in HwlDegradeThickTileMode()1372 case ADDR_TM_1D_TILED_THIN1://fall through in DispatchComputeSurfaceAddrFromCoord()2234 case ADDR_TM_1D_TILED_THIN1://fall through in DispatchComputeSurfaceCoordFromAddr()
3345 tileMode = ADDR_TM_1D_TILED_THIN1; in HwlOptimizeTileMode()
172 ADDR_TM_1D_TILED_THIN1 = 2, ///< Linear array of 8x8 tiles enumerator
3661 ADDR_TM_1D_TILED_THIN1 : ADDR_TM_1D_TILED_THICK; in OptimizeTileMode()3707 ADDR_TM_1D_TILED_THIN1 : ADDR_TM_1D_TILED_THICK; in OptimizeTileMode()3725 ADDR_TM_1D_TILED_THIN1 : ADDR_TM_1D_TILED_THICK; in OptimizeTileMode()3741 pInOut->tileMode = ADDR_TM_1D_TILED_THIN1; in OptimizeTileMode()
548 case ADDR_TM_1D_TILED_THIN1: in gfx6_compute_level()878 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1; in gfx6_compute_surface()