Searched refs:ADDR_TM_3D_TILED_THIN1 (Results 1 – 5 of 5) sorted by relevance
184 case ADDR_TM_3D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()1131 case ADDR_TM_3D_TILED_THIN1: in ComputeSurfaceMipLevelTileMode()1257 expTileMode = ADDR_TM_3D_TILED_THIN1; in HwlDegradeThickTileMode()1275 expTileMode = ADDR_TM_3D_TILED_THIN1; in HwlDegradeThickTileMode()1389 case ADDR_TM_3D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()2254 case ADDR_TM_3D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()2514 case ADDR_TM_3D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()3028 case ADDR_TM_3D_TILED_THIN1: // fall through in ComputeBankFromCoord()3050 case ADDR_TM_3D_TILED_THIN1: //fall through in ComputeBankFromCoord()3123 case ADDR_TM_3D_TILED_THIN1: //fall through in ComputePipeRotation()[all …]
800 tileMode == ADDR_TM_3D_TILED_THIN1 || in HwlComputeFmaskInfo()806 ADDR_ASSERT(m_tileTable[15].mode == ADDR_TM_3D_TILED_THIN1); in HwlComputeFmaskInfo()1071 tileMode = ADDR_TM_3D_TILED_THIN1; in HwlOverrideTileMode()1293 else if (tileMode == ADDR_TM_3D_TILED_THIN1 || tileMode == ADDR_TM_PRT_3D_TILED_THIN1) in HwlSetupTileInfo()1415 case ADDR_TM_3D_TILED_THIN1: in HwlSetupTileInfo()
798 case ADDR_TM_3D_TILED_THIN1: //fall through thin in ComputePipeFromCoord()3842 (tileConfig.mode == ADDR_TM_3D_TILED_THIN1) || in IsEquationSupported()
182 ADDR_TM_3D_TILED_THIN1 = 12, ///< Macro tiling w/ pipe rotation between slices enumerator
3802 tileMode = ADDR_TM_3D_TILED_THIN1; in DegradeLargeThickTile()