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Searched refs:ADDR_TM_LINEAR_ALIGNED (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/amd/addrlib/inc/
Daddrtypes.h171 ADDR_TM_LINEAR_ALIGNED = 1, ///< Requests pitch or slice to be multiple of 64 pixels enumerator
/external/mesa3d/src/amd/addrlib/src/r800/
Dciaddrlib.cpp555 else if (mode == ADDR_TM_LINEAR_ALIGNED) in HwlPostCheckTileIndex()
1559 else if (tileMode == ADDR_TM_LINEAR_ALIGNED) in HwlSetupTileInfo()
1699 ADDR_ASSERT(m_tileTable[TILEINDEX_LINEAR_ALIGNED].mode == ADDR_TM_LINEAR_ALIGNED); in InitTileSettingTable()
Degbaddrlib.cpp173 case ADDR_TM_LINEAR_ALIGNED: in DispatchComputeSurfaceInfo()
684 case ADDR_TM_LINEAR_ALIGNED: in ComputeSurfaceAlignmentsLinear()
1361 case ADDR_TM_LINEAR_ALIGNED: in DispatchComputeSurfaceAddrFromCoord()
2222 case ADDR_TM_LINEAR_ALIGNED: in DispatchComputeSurfaceCoordFromAddr()
Dsiaddrlib.cpp2204 if (tileMode == ADDR_TM_LINEAR_ALIGNED) in HwlSetupTileInfo()
2951 else if (mode == ADDR_TM_LINEAR_ALIGNED) in HwlPostCheckTileIndex()
3148 ADDR_ASSERT(m_tileTable[TILEINDEX_LINEAR_ALIGNED].mode == ADDR_TM_LINEAR_ALIGNED); in InitTileSettingTable()
/external/mesa3d/src/amd/common/
Dac_surface.c495 if (config->info.levels == 1 && AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED && in gfx6_compute_level()
506 assert(AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED); in gfx6_compute_level()
545 case ADDR_TM_LINEAR_ALIGNED: in gfx6_compute_level()
875 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED; in gfx6_compute_surface()
/external/mesa3d/src/amd/addrlib/src/core/
Daddrlib1.cpp3383 pIn->tileMode == ADDR_TM_LINEAR_ALIGNED) in HwlPreHandleBaseLvl3xPitch()
3414 pIn->tileMode == ADDR_TM_LINEAR_ALIGNED) in HwlPostHandleBaseLvl3xPitch()
3654 tileMode = ADDR_TM_LINEAR_ALIGNED; in OptimizeTileMode()