Searched refs:ADDR_TM_PRT_TILED_THIN1 (Results 1 – 5 of 5) sorted by relevance
801 tileMode == ADDR_TM_PRT_TILED_THIN1 || in HwlComputeFmaskInfo()950 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlOptimizeTileMode()976 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlOptimizeTileMode()1024 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlOverrideTileMode()1075 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlOverrideTileMode()1186 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlSelectTileMode()1232 tileMode = ADDR_TM_PRT_TILED_THIN1; in HwlSetPrtTileMode()1377 case ADDR_TM_PRT_TILED_THIN1: in HwlSetupTileInfo()1396 case ADDR_TM_PRT_TILED_THIN1: in HwlSetupTileInfo()1418 case ADDR_TM_PRT_TILED_THIN1: in HwlSetupTileInfo()[all …]
188 case ADDR_TM_PRT_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()1132 case ADDR_TM_PRT_TILED_THIN1: in ComputeSurfaceMipLevelTileMode()1393 case ADDR_TM_PRT_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()2258 case ADDR_TM_PRT_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()
3379 case ADDR_TM_PRT_TILED_THIN1: in HwlOverrideTileMode()
189 ADDR_TM_PRT_TILED_THIN1 = 19, ///< No bank/pipe rotation or hashing beyond macrotile size enumerator
3806 tileMode = ADDR_TM_PRT_TILED_THIN1; in DegradeLargeThickTile()