| /external/llvm-project/llvm/test/CodeGen/RISCV/ |
| D | select-optimize-multiple.mir | 52 ; RV32I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
54 ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.2
60 ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.4
74 ; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
76 ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.2
82 ; RV64I: BNE [[ANDI]], [[COPY4]], %bb.4
93 %5:gpr = ANDI %0, 1
138 ; RV32I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
142 ; RV32I: BNE [[ANDI]], [[COPY4]], %bb.2
159 ; RV64I: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/AVR/ |
| D | and.ll | 70 ; Per PR 31345, we optimize away ANDI Rd, 0xff
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_32.c | 96 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xff), DR(dst)); in emit_single_op()
115 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xffff), DR(dst)); in emit_single_op()
391 EMIT_LOGICAL(ANDI, AND); in emit_single_op()
|
| D | sljitNativeMIPS_64.c | 182 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xff), DR(dst)); in emit_single_op()
197 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xffff), DR(dst)); in emit_single_op()
487 EMIT_LOGICAL(ANDI, AND); in emit_single_op()
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| D | sljitNativePPC_32.c | 183 return push_inst(compiler, ANDI | S(src1) | A(dst) | compiler->imm); in emit_single_op()
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| D | sljitNativeARM_T2_32.c | 106 #define ANDI 0xf0000000 macro
700 return push_inst32(compiler, ANDI | (flags & SET_FLAGS) | RD4(dst) | RN4(reg) | nimm); in emit_op_imm()
2203 FAIL_IF(push_inst32(compiler, ANDI | RN4(dst_r) | RD4(dst_r) | 1)); in sljit_emit_op_flags()
2204 FAIL_IF(push_inst32(compiler, ANDI | RN4(dst_r) | RD4(dst_r) | 0)); in sljit_emit_op_flags()
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| D | sljitNativePPC_64.c | 332 return push_inst(compiler, ANDI | S(src1) | A(dst) | compiler->imm); in emit_single_op()
|
| D | sljitNativeARM_64.c | 74 #define ANDI 0x92000000 macro
682 return push_inst(compiler, (ANDI ^ inv_bits) | RD(dst) | RN(reg) | inst_bits); in emit_op_imm()
|
| D | sljitNativeMIPS_common.c | 135 #define ANDI (HI(12)) macro
2151 FAIL_IF(push_inst(compiler, ANDI | SA(dst_ar) | TA(dst_ar) | IMM(1), dst_ar)); in sljit_emit_op_flags()
|
| D | sljitNativePPC_common.c | 147 #define ANDI (HI(28)) macro
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | p8-scalar_vector_conversions.ll | 681 ; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8
682 ; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]]
715 ; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8
716 ; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]]
1032 ; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4
1033 ; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1
1068 ; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4
1069 ; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1
|
| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoB.td | 62 // Checks if this mask has a single 0 bit and cannot be used with ANDI.
483 def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>;
488 def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>;
799 (FSL GPR:$rs1, (ANDI GPR:$rs2, 31), GPR:$rs3)>;
801 (FSR GPR:$rs1, (ANDI GPR:$rs2, 31), GPR:$rs3)>;
805 (FSL GPR:$rs1, (ANDI GPR:$rs2, 63), GPR:$rs3)>;
807 (FSR GPR:$rs1, (ANDI GPR:$rs2, 63), GPR:$rs3)>;
|
| D | RISCVFrameLowering.cpp | 473 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg) in emitPrologue()
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| D | RISCVInstrInfo.td | 470 def ANDI : ALU_ri<0b111, "andi">;
770 (ANDI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
863 def : PatGprSimm12<and, ANDI>;
|
| D | RISCVInstrInfoC.td | 831 def : CompressPat<(ANDI GPRC:$rs1, GPRC:$rs1, simm6:$imm),
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVFrameLowering.cpp | 218 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg) in emitPrologue()
|
| D | RISCVInstrInfo.td | 420 def ANDI : ALU_ri<0b111, "andi">;
708 (ANDI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
801 def : PatGprSimm12<and, ANDI>;
|
| D | RISCVInstrInfoC.td | 826 def : CompressPat<(ANDI GPRC:$rs1, GPRC:$rs1, simm6:$imm),
|
| /external/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.td | 634 // ANDI Rd+1:Rd, K+1:K
1657 // Alias for `ANDI Rd, COM(K)` where COM(K) is the compliment of K.
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | P9InstrResources.td | 133 (instregex "ANDI(S)?(8)?(_rec)?$"),
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | P9InstrResources.td | 133 (instregex "ANDI(S)?(8)?(_rec)?$"),
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.td | 676 // ANDI Rd+1:Rd, K+1:K
|
| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.td | 682 // ANDI Rd+1:Rd, K+1:K
|
| /external/icu/icu4j/perf-tests/data/collation/ |
| D | TestNames_SerbianSH.txt | 6171 ANDIĆ SVETOZAR
6172 ANDIĆ VLADIMIR
|