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Searched refs:ANY_EXTEND_VECTOR_INREG (Results 1 – 25 of 34) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h422 ANY_EXTEND_VECTOR_INREG, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h558 ANY_EXTEND_VECTOR_INREG, enumerator
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h707 ANY_EXTEND_VECTOR_INREG, enumerator
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp436 case ISD::ANY_EXTEND_VECTOR_INREG: in LegalizeOp()
732 case ISD::ANY_EXTEND_VECTOR_INREG: in Expand()
1018 SDValue Op = DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Src); in ExpandSIGN_EXTEND_VECTOR_INREG()
DLegalizeVectorTypes.cpp67 case ISD::ANY_EXTEND_VECTOR_INREG: in ScalarizeVectorResult()
402 case ISD::ANY_EXTEND_VECTOR_INREG: in ScalarizeVecRes_VecInregOp()
918 case ISD::ANY_EXTEND_VECTOR_INREG: in SplitVectorResult()
2111 case ISD::ANY_EXTEND_VECTOR_INREG: in SplitVectorOperand()
2943 case ISD::ANY_EXTEND_VECTOR_INREG: in WidenVectorResult()
3418 return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, WidenVT, InOp); in WidenVecRes_Convert()
3524 case ISD::ANY_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
3538 case ISD::ANY_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
4482 return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, InOp); in WidenVecOp_EXTEND()
DSelectionDAGDumper.cpp333 case ISD::ANY_EXTEND_VECTOR_INREG: return "any_extend_vector_inreg"; in getOperationName()
DTargetLowering.cpp788 case ISD::ANY_EXTEND_VECTOR_INREG: in SimplifyMultipleUseDemandedBits()
1866 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND; in SimplifyDemandedBits()
1904 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND; in SimplifyDemandedBits()
1940 case ISD::ANY_EXTEND_VECTOR_INREG: { in SimplifyDemandedBits()
1945 bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG; in SimplifyDemandedBits()
2746 case ISD::ANY_EXTEND_VECTOR_INREG: in SimplifyDemandedVectorElts()
2759 if (Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG && in SimplifyDemandedVectorElts()
DLegalizeIntegerTypes.cpp112 case ISD::ANY_EXTEND_VECTOR_INREG: in PromoteIntegerResult()
4765 case ISD::ANY_EXTEND_VECTOR_INREG: in PromoteIntRes_EXTEND_VECTOR_INREG()
DSelectionDAG.cpp3129 case ISD::ANY_EXTEND_VECTOR_INREG: { in computeKnownBits()
4671 case ISD::ANY_EXTEND_VECTOR_INREG: in getNode()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp105 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, T, Custom); in initializeHVXLowering()
138 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, T, Custom); in initializeHVXLowering()
1436 assert(Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG); in LowerHvxExtend()
1580 case ISD::ANY_EXTEND_VECTOR_INREG: return LowerHvxExtend(Op, DAG); in LowerHvxOperation()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp328 case ISD::ANY_EXTEND_VECTOR_INREG: in LegalizeOp()
681 case ISD::ANY_EXTEND_VECTOR_INREG: in Expand()
DSelectionDAGDumper.cpp245 case ISD::ANY_EXTEND_VECTOR_INREG: return "any_extend_vector_inreg"; in getOperationName()
DLegalizeVectorTypes.cpp621 case ISD::ANY_EXTEND_VECTOR_INREG: in SplitVectorResult()
2129 case ISD::ANY_EXTEND_VECTOR_INREG: in WidenVectorResult()
2439 case ISD::ANY_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
2455 case ISD::ANY_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
DLegalizeIntegerTypes.cpp105 case ISD::ANY_EXTEND_VECTOR_INREG: in PromoteIntegerResult()
3363 case ISD::ANY_EXTEND_VECTOR_INREG: in PromoteIntRes_EXTEND_VECTOR_INREG()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp439 case ISD::ANY_EXTEND_VECTOR_INREG: in LegalizeOp()
851 case ISD::ANY_EXTEND_VECTOR_INREG: in Expand()
1118 SDValue Op = DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Src); in ExpandSIGN_EXTEND_VECTOR_INREG()
DLegalizeVectorTypes.cpp66 case ISD::ANY_EXTEND_VECTOR_INREG: in ScalarizeVectorResult()
392 case ISD::ANY_EXTEND_VECTOR_INREG: in ScalarizeVecRes_VecInregOp()
859 case ISD::ANY_EXTEND_VECTOR_INREG: in SplitVectorResult()
1978 case ISD::ANY_EXTEND_VECTOR_INREG: in SplitVectorOperand()
2785 case ISD::ANY_EXTEND_VECTOR_INREG: in WidenVectorResult()
3251 return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, WidenVT, InOp); in WidenVecRes_Convert()
3361 case ISD::ANY_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
3375 case ISD::ANY_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
4315 return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, InOp); in WidenVecOp_EXTEND()
DSelectionDAGDumper.cpp323 case ISD::ANY_EXTEND_VECTOR_INREG: return "any_extend_vector_inreg"; in getOperationName()
DTargetLowering.cpp1695 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND; in SimplifyDemandedBits()
1728 IsVecInReg ? ISD::ANY_EXTEND_VECTOR_INREG : ISD::ANY_EXTEND; in SimplifyDemandedBits()
1759 case ISD::ANY_EXTEND_VECTOR_INREG: { in SimplifyDemandedBits()
1764 bool IsVecInReg = Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG; in SimplifyDemandedBits()
2512 case ISD::ANY_EXTEND_VECTOR_INREG: in SimplifyDemandedVectorElts()
2525 if (Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG && in SimplifyDemandedVectorElts()
DLegalizeIntegerTypes.cpp110 case ISD::ANY_EXTEND_VECTOR_INREG: in PromoteIntegerResult()
4360 case ISD::ANY_EXTEND_VECTOR_INREG: in PromoteIntRes_EXTEND_VECTOR_INREG()
DDAGCombiner.cpp10599 if ((N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG || in visitSIGN_EXTEND_INREG()
18915 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND_VECTOR_INREG, OutVT)) in combineShuffleToVectorExtend()
18917 DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, in combineShuffleToVectorExtend()
18941 if (Opcode != ISD::ANY_EXTEND_VECTOR_INREG && in combineTruncationShuffle()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp129 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, T, Custom); in initializeHVXLowering()
162 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, T, Custom); in initializeHVXLowering()
1633 assert(Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG); in LowerHvxExtend()
2080 case ISD::ANY_EXTEND_VECTOR_INREG: return LowerHvxExtend(Op, DAG); in LowerHvxOperation()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetLoweringBase.cpp697 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp898 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
/external/llvm-project/llvm/lib/CodeGen/
DTargetLoweringBase.cpp815 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp879 case ISD::ANY_EXTEND_VECTOR_INREG: { in PreprocessISelDAG()

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