| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | msr-it-block.ll | 23 ; V7A: msr APSR_nzcvq, {{r[0-9]+}}
24 ; V7A: msr APSR_nzcvq, {{r[0-9]+}}
44 ; V7A: msr APSR_nzcvq, {{r[0-9]+}}
45 ; V7A: msr APSR_nzcvq, {{r[0-9]+}}
|
| D | special-reg-acore.ll | 30 ; ACORE: msr APSR_nzcvq, r0
36 ; ACORE: msr APSR_nzcvq, r0
|
| D | special-reg.ll | 55 ; ACORE: msr APSR_nzcvq, r0
|
| D | copy-cpsr.ll | 24 ; CHECK-ARM: msr APSR_nzcvq, [[TMP]] @ encoding: [0x0{{[0-9a-f]}},0xf0,0x28,0xe1]
|
| /external/llvm-project/compiler-rt/lib/builtins/arm/ |
| D | aeabi_cfcmp.S | 55 msr APSR_nzcvq, ip
57 msr APSR_nzcvq, #APSR_C
117 msr APSR_nzcvq, ip
|
| D | aeabi_cdcmp.S | 55 msr APSR_nzcvq, ip
57 msr APSR_nzcvq, #APSR_C
117 msr APSR_nzcvq, ip
|
| /external/llvm/test/CodeGen/ARM/ |
| D | special-reg-acore.ll | 30 ; ACORE: msr APSR_nzcvq, r0
36 ; ACORE: msr APSR_nzcvq, r0
|
| D | special-reg.ll | 55 ; ACORE: msr APSR_nzcvq, r0
|
| D | copy-cpsr.ll | 24 ; CHECK-ARM: msr APSR_nzcvq, [[TMP]] @ encoding: [0x0{{[0-9a-f]}},0xf0,0x28,0xe1]
|
| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.cc | 222 case APSR_nzcvq: in GetName()
|
| /external/vixl/test/aarch32/ |
| D | test-simulator-cond-rd-rn-rm-q-t32.cc | 461 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
473 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
|
| D | test-simulator-cond-rd-rn-rm-sel-t32.cc | 454 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
466 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
|
| D | test-simulator-cond-rd-rn-rm-sel-a32.cc | 454 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
466 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
|
| D | test-simulator-cond-rd-rn-rm-q-a32.cc | 461 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
473 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
|
| D | test-simulator-cond-rd-rn-rm-ge-a32.cc | 477 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
489 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
|
| D | test-simulator-cond-rd-rn-rm-ge-t32.cc | 477 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
489 __ Msr(APSR_nzcvq, q_bit); in TestHelper()
|
| D | test-simulator-cond-rd-operand-const-a32.cc | 523 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
|
| D | test-simulator-cond-rd-operand-imm16-t32.cc | 476 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
|
| D | test-simulator-cond-rd-operand-const-t32.cc | 638 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
|
| D | test-simulator-cond-rd-operand-rn-a32.cc | 560 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
|
| D | test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 625 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
|
| D | test-simulator-cond-rd-operand-rn-t32.cc | 560 __ Msr(APSR_nzcvq, nzcv_bits); in TestHelper()
|
| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | cortex-a57-basic-instructions.s | 310 msr APSR_nzcvq, #5
311 msr APSR_nzcvq, #5
322 msr APSR_nzcvq, #2147483658
326 msr APSR_nzcvq, r0
327 msr APSR_nzcvq, r0
1180 # CHECK-NEXT: 0 0 0.00 U msr APSR_nzcvq, #5
1181 # CHECK-NEXT: 0 0 0.00 U msr APSR_nzcvq, #5
1192 # CHECK-NEXT: 0 0 0.00 U msr APSR_nzcvq, #2147483658
1196 # CHECK-NEXT: 0 0 0.00 U msr APSR_nzcvq, r0
1197 # CHECK-NEXT: 0 0 0.00 U msr APSR_nzcvq, r0
[all …]
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1458 msr APSR_nzcvq, #5
1470 msr APSR_nzcvq, #42, #2
1477 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1478 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1479 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1481 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1482 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1494 @ CHECK: msr APSR_nzcvq, #2147483658 @ encoding: [0x2a,0xf1,0x28,0xe3]
1504 msr APSR_nzcvq, r0
1516 @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
[all …]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 1428 msr APSR_nzcvq, #5
1440 msr APSR_nzcvq, #42, #2
1447 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1448 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1449 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1451 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1452 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
1464 @ CHECK: msr APSR_nzcvq, #2147483658 @ encoding: [0x2a,0xf1,0x28,0xe3]
1474 msr APSR_nzcvq, r0
1486 @ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
[all …]
|