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Searched refs:ARG3 (Results 1 – 25 of 69) sorted by relevance

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/external/llvm-project/mlir/test/Dialect/Linalg/
Dtile-parallel-reduce.mlir17 // CHECK: scf.parallel (%[[ARG3:.*]], %[[ARG4:.*]]) =
21 // CHECK: %[[SV1:.*]] = subview %{{.*}}[%[[ARG3]], %[[ARG5]]]
23 // CHECK: %[[SV3:.*]] = subview %{{.*}}[%[[ARG3]], %[[ARG4]]]
28 // TILE1: scf.parallel (%[[ARG3:.*]]) =
30 // TILE1: %[[SV1:.*]] = subview %{{.*}}[%[[ARG3]], 0]
31 // TILE1: %[[SV3:.*]] = subview %{{.*}}[%[[ARG3]], 0]
38 // TILE2: scf.parallel (%[[ARG3:.*]], %[[ARG4:.*]]) =
40 // TILE2: %[[SV1:.*]] = subview %{{.*}}[%[[ARG3]], 0]
42 // TILE2: %[[SV3:.*]] = subview %{{.*}}[%[[ARG3]], %[[ARG4]]]
77 // CHECK: scf.for %[[ARG3:.*]] =
[all …]
Dtile-and-distribute.mlir17 // CHECK: scf.for %[[ARG3:.*]] =
19 // CHECK: %[[SV1:.*]] = subview %[[ARG0]][%[[OFFSETY]], %[[ARG3]]]
21 // CHECK: %[[SV2:.*]] = subview %[[ARG1]][%[[ARG3]], %[[OFFSETX]]]
49 // CHECK: scf.for %[[ARG3:.*]] =
51 // CHECK: %[[SV1:.*]] = subview %[[ARG0]][%[[OFFSETY]], %[[ARG3]]]
53 // CHECK: %[[SV2:.*]] = subview %[[ARG1]][%[[ARG3]], %[[OFFSETX]]]
81 // CHECK: scf.parallel (%[[ARG3:.*]], %[[ARG4:.*]]) = (%[[LBY]], %[[LBX]]) to (%{{.*}}, %{{.*}…
83 // CHECK: %[[SV1:.*]] = subview %[[ARG0]][%[[ARG3]], %[[ARG5]]]
85 // CHECK: %[[SV3:.*]] = subview %[[ARG2]][%[[ARG3]], %[[ARG4]]]
107 // CHECK: scf.for %[[ARG3:.*]] =
[all …]
Dtile-simple-conv.mlir28 // CHECK: scf.for %[[ARG3:.*]] = %[[C0]] to %[[T2]] step %[[C2]]
32 // CHECK: %[[T6:.*]] = affine.min #[[MAP0]](%[[ARG3]])[%[[T5]]]
38 // CHECK: %[[SV1:.*]] = subview %[[ARG1]][%[[ARG3]], %[[ARG4]], %[[ARG5]], 0]
41 // CHECK: %[[T14:.*]] = affine.min #[[MAP0]](%[[ARG3]])[%[[T13]]]
47 // CHECK: %[[SV2:.*]] = subview %[[ARG2]][%[[ARG3]], %[[ARG4]], %[[ARG5]], 0]
Dfusion-pattern.mlir93 // CHECK-SAME: %[[ARG3:[a-zA-Z0-9_]+]]: memref<?x?xf32>
109 // CHECK: %[[M:.+]] = dim %[[ARG3]], %[[C0]]
110 // CHECK: %[[N_2:.+]] = dim %[[ARG3]], %[[C1]]
112 // CHECK: %[[SV2:.+]] = subview %[[ARG3]][0, %[[IV0]]]
171 // CHECK-SAME: %[[ARG3:[a-zA-Z0-9_]+]]: memref<?x?xf32>
180 // CHECK: linalg.fill(%[[ARG3]], %[[CST]])
189 // CHECK: %[[M_2:.+]] = dim %[[ARG3]], %[[C0]]
191 // CHECK: %[[N:.+]] = dim %[[ARG3]], %[[C1]]
192 // CHECK: %[[SV2:.+]] = subview %[[ARG3]][%[[IV0]], 0]
194 // CHECK: %[[SV2_2:.+]] = subview %[[ARG3]][%[[IV0]], 0]
[all …]
Dfusion-sequence.mlir36 // CHECK-SAME: %[[ARG3:[a-zA-Z0-9_]+]]: memref<?x?xf32>
41 // CHECK-DAG: %[[SV_ARG3:.+]] = subview %[[ARG3]][%[[IV0]], %[[IV1]]]
90 // CHECK-SAME: %[[ARG3:[a-zA-Z0-9_]+]]: memref<?x?xf32>
128 // CHECK: linalg.matmul ins(%[[SV_ALLOC2]], %[[ARG3]]
Dreshape_fusion.mlir229 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9]+]]: index, %[[ARG3:[a-zA-Z0-9]+]]: index,
232 // CHECK: %[[T3:.+]] = affine.apply #[[MAP]](%[[ARG2]], %[[ARG3]])
272 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9]+]]: index, %[[ARG3:[a-zA-Z0-9]+]]: index,
275 // CHECK: %[[T3:.+]] = affine.apply #[[MAP]](%[[ARG3]], %[[ARG4]], %[[ARG5]])
334 // CHECK-SAME: %[[ARG2:[a-zA-Z0-9]+]]: index, %[[ARG3:[a-zA-Z0-9]+]]: index,
338 // CHECK-DAG: %[[T3:.+]] = affine.apply #[[MAP5]](%[[ARG2]], %[[ARG3]])
385 // CHECK-SAME: %[[ARG3:[a-zA-Z0-9]+]]: index,
391 // CHECK: %[[T3:.+]] = index_cast %[[ARG3]] : index to i32
/external/llvm-project/mlir/test/Conversion/StandardToSPIRV/
Dlegalization.mlir4 // CHECK-SAME: [[ARG0:%.*]]: memref<12x32xf32>, [[ARG1:%.*]]: index, [[ARG2:%.*]]: index, [[ARG3:%.…
9 // CHECK: [[STRIDE1:%.*]] = muli [[ARG3]], [[C2]] : index
20 // CHECK-SAME: [[ARG0:%.*]]: memref<12x32xf32>, [[ARG1:%.*]]: index, [[ARG2:%.*]]: index, [[ARG3:%.…
23 // CHECK: [[STRIDE1:%.*]] = muli [[ARG3]], [[ARG5]] : index
35 // CHECK-SAME: [[ARG0:%.*]]: memref<12x32xf32>, [[ARG1:%.*]]: index, [[ARG2:%.*]]: index, [[ARG3:%.…
40 // CHECK: [[STRIDE1:%.*]] = muli [[ARG3]], [[C2]] : index
52 // CHECK-SAME: [[ARG0:%.*]]: memref<12x32xf32>, [[ARG1:%.*]]: index, [[ARG2:%.*]]: index, [[ARG3:%.…
55 // CHECK: [[STRIDE1:%.*]] = muli [[ARG3]], [[ARG5]] : index
67 // CHECK-SAME: [[ARG0:%.*]]: memref<12x32xf32>, [[ARG1:%.*]]: index, [[ARG2:%.*]]: index, [[ARG3:%.…
73 // CHECK: [[STRIDE1:%.*]] = muli [[ARG3]], [[C2]] : index
[all …]
Dsubview-to-spirv.mlir13 // CHECK-SAME: %[[ARG3:[a-zA-Z0-9_]*]]: index
20 // CHECK: %[[T0:.*]] = muli %[[ARG3]], %[[C3]]
26 // CHECK: %[[T6:.*]] = muli %[[ARG3]], %[[C3]]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Daarch64-sve-asm.ll9 ; CHECK: [[ARG3:%[0-9]+]]:zpr = COPY [[ARG2]]
20 ; CHECK: [[ARG3:%[0-9]+]]:zpr = COPY [[ARG2]]
31 ; CHECK: [[ARG3:%[0-9]+]]:zpr = COPY [[ARG2]]
42 ; CHECK: [[ARG3:%[0-9]+]]:zpr = COPY [[ARG2]]
53 ; CHECK: [[ARG3:%[0-9]+]]:ppr = COPY $p0
54 ; CHECK: [[ARG4:%[0-9]+]]:ppr_3b = COPY [[ARG3]]
64 ; CHECK: [[ARG3:%[0-9]+]]:ppr = COPY [[ARG2]]
66 ; CHECK: INLINEASM {{.*}} [[ARG3]]
/external/llvm-project/llvm/test/Transforms/Attributor/
Dnofree.ll371 ; ATTRIBUTOR-SAME: (i8* nofree [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* nofree [[ARG3:%.*]], i8* [[ARG4:…
372 …TOR-NEXT: call void @llvm.assume(i1 true) #11 [ "nofree"(i8* [[ARG1]]), "nofree"(i8* [[ARG3]]) ]
373 ; ATTRIBUTOR-NEXT: call void @unknown(i8* nofree [[ARG1]], i8* [[ARG2]], i8* nofree [[ARG3]], i8…
377 ; IS__TUNIT____-SAME: (i8* nofree [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* nofree [[ARG3:%.*]], i8* [[AR…
378 …ll void @llvm.assume(i1 noundef true) [[ATTR11]] [ "nofree"(i8* [[ARG1]]), "nofree"(i8* [[ARG3]]) ]
379 ; IS__TUNIT____-NEXT: call void @unknown(i8* nofree [[ARG1]], i8* [[ARG2]], i8* nofree [[ARG3]],…
383 ; IS__CGSCC____-SAME: (i8* nofree [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* nofree [[ARG3:%.*]], i8* [[AR…
384 …ll void @llvm.assume(i1 noundef true) [[ATTR12]] [ "nofree"(i8* [[ARG1]]), "nofree"(i8* [[ARG3]]) ]
385 ; IS__CGSCC____-NEXT: call void @unknown(i8* nofree [[ARG1]], i8* [[ARG2]], i8* nofree [[ARG3]],…
394 ; ATTRIBUTOR-SAME: (i8* [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* [[ARG3:%.*]], i8* [[ARG4:%.*]])
[all …]
Ddereferenceable-1.ll1012 …nceable_or_null(31) [[ARG2:%.*]], i8* nocapture nofree nonnull readnone [[ARG3:%.*]], i8* nocaptur…
1018 …nceable_or_null(31) [[ARG2:%.*]], i8* nocapture nofree nonnull readnone [[ARG3:%.*]], i8* nocaptur…
1019 … call void @llvm.assume(i1 noundef true) [[ATTR7:#.*]] [ "nonnull"(i8* [[ARG3]]), "dereferenceabl…
1024 …nceable_or_null(31) [[ARG2:%.*]], i8* nocapture nofree nonnull readnone [[ARG3:%.*]], i8* nocaptur…
1025 … call void @llvm.assume(i1 noundef true) [[ATTR8:#.*]] [ "nonnull"(i8* [[ARG3]]), "dereferenceabl…
1030 …nceable_or_null(31) [[ARG2:%.*]], i8* nocapture nofree nonnull readnone [[ARG3:%.*]], i8* nocaptur…
1031 … call void @llvm.assume(i1 noundef true) [[ATTR9:#.*]] [ "nonnull"(i8* [[ARG3]]), "dereferenceabl…
1041 …ARG1:%.*]], i8* nocapture nofree readnone [[ARG2:%.*]], i8* nocapture nofree readnone [[ARG3:%.*]])
1047 …G1:%.*]], i8* nocapture nofree readnone [[ARG2:%.*]], i8* nocapture nofree readnone [[ARG3:%.*]]) {
1049 …64 101), "dereferenceable"(i8* [[ARG2]], i64 -2), "dereferenceable_or_null"(i8* [[ARG3]], i64 31) ]
[all …]
/external/llvm-project/mlir/test/Dialect/Affine/
Dloop-tiling-parametric.mlir19 // CHECK-NEXT: affine.for [[ARG3:%arg[0-9]+]] = 0 to [[UBO0]](){{.*}}[[ARG0]]
22 …T: affine.for %[[I:.*]] = [[LBI]]{{.*}}[[ARG3]]{{.*}}[[ARG0]]{{.*}} to min [[UBI0]]{{.*}}[…
48 // CHECK-NEXT: affine.for [[ARG3:%arg[0-9]+]] = 0 to [[UBO0]](){{.*}}[[ARG0]]{{.*}}step 4
51 …T: affine.for %[[I:.*]] = [[LBI]]{{.*}}[[ARG3]]{{.*}}[[ARG0]]{{.*}} to min [[UBI0]]{{.*}}[…
116 // CHECK-NEXT: affine.for [[ARG3:%arg[0-9+]]] = 8 to [[UBO0]]{{.*}}[[ARG0]]{{.*}}
119 …ECK-NEXT: affine.for %[[I:.*]] = [[LBI0]]([[ARG3]]){{.*}}[[ARG0]]{{.*}} to min [[UBI0]]([[A…
144 // CHECK-NEXT: affine.for [[ARG3:%arg[0-9]+]] = 0 to [[UBO0]](){{.*}}[[ARG0]]{{.*}}
147 …T: affine.for %[[I:.*]] = [[LBI]]{{.*}}[[ARG3]]{{.*}}[[ARG0]]{{.*}} to min [[UBI0]]{{.*}}[…
180 // CHECK-NEXT: affine.for [[ARG3:%arg[0-9]+]] = 0 to [[UBO0]](){{.*}}[[ARG1]]{{.*}}
182 … affine.for %[[I1:.*]] = [[LBI0]]{{.*}}[[ARG3]]{{.*}}[[ARG1]]{{.*}} to min [[UBI0]]{{.*}}[…
[all …]
/external/llvm-project/mlir/test/Conversion/OpenMPToLLVM/
Dconvert-to-llvmir.mlir17 // CHECK-NEXT: ^[[BB2]](%[[ARG3:[0-9]+]]: !llvm.i64, %[[ARG4:[0-9]+]]: !llvm.i64):
19 // CHECK-NEXT: llvm.br ^[[BB1]](%[[ARG3]], %[[ARG4]] : !llvm.i64, !llvm.i64)
33 // CHECK: (%[[ARG0:.*]]: !llvm.i64, %[[ARG1:.*]]: !llvm.i64, %[[ARG2:.*]]: !llvm.i64, %[[ARG3:.*]]:…
38 // CHECK: (%[[ARG0]], %[[ARG1]], %[[ARG2]], %[[ARG3]], %[[ARG4]], %[[ARG5]])
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/
Dcmsis_armcc.h721 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ argument
722 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
724 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ argument
725 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
727 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ argument
728 ((int64_t)(ARG3) << 32U) ) >> 32U))
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/
Dcmsis_armcc.h721 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ argument
722 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
724 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ argument
725 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
727 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ argument
728 ((int64_t)(ARG3) << 32U) ) >> 32U))
/external/tensorflow/tensorflow/compiler/mlir/xla/tests/hlo_to_lhlo_with_xla/
Dgpu_ops.mlir7 // CHECK-SAME: %[[ARG3:.*]]: memref<36xi8> {lmhlo.alloc = 0
8 // CHECK: %[[VIEW0:.*]] = std.view %[[ARG3]]{{.*}} : memref<36xi8> to memref<3x3xi32>
10 // CHECK: %[[VIEW1:.*]] = std.view %[[ARG3]]{{.*}} : memref<36xi8> to memref<3x3xi32>
/external/strace/tests-mx32/
Dfutex.c90 ARG3 = 1 << 0, enumerator
132 if (((1 << i) == ARG3) || ((1 << i) == ARG6) || in invalid_op()
369 CHECK_INVALID_CLOCKRT(FUTEX_WAKE, ARG3, "%u"); in main()
406 CHECK_INVALID_CLOCKRT(FUTEX_WAKE_BITSET, ARG3 | ARG6, "%u", "%#x"); in main()
429 CHECK_INVALID_CLOCKRT(FUTEX_FD, ARG3, "%u"); in main()
463 CHECK_INVALID_CLOCKRT(FUTEX_REQUEUE, ARG3 | ARG4 | ARG5, "%u", "%u", in main()
511 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE, ARG3 | ARG4 | ARG5 | ARG6, in main()
624 CHECK_INVALID_CLOCKRT(FUTEX_WAKE_OP, ARG3 | ARG4 | ARG5 | ARG6, in main()
787 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE_PI, ARG3 | ARG4 | ARG5 | ARG6, in main()
/external/strace/tests-m32/
Dfutex.c90 ARG3 = 1 << 0, enumerator
132 if (((1 << i) == ARG3) || ((1 << i) == ARG6) || in invalid_op()
369 CHECK_INVALID_CLOCKRT(FUTEX_WAKE, ARG3, "%u"); in main()
406 CHECK_INVALID_CLOCKRT(FUTEX_WAKE_BITSET, ARG3 | ARG6, "%u", "%#x"); in main()
429 CHECK_INVALID_CLOCKRT(FUTEX_FD, ARG3, "%u"); in main()
463 CHECK_INVALID_CLOCKRT(FUTEX_REQUEUE, ARG3 | ARG4 | ARG5, "%u", "%u", in main()
511 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE, ARG3 | ARG4 | ARG5 | ARG6, in main()
624 CHECK_INVALID_CLOCKRT(FUTEX_WAKE_OP, ARG3 | ARG4 | ARG5 | ARG6, in main()
787 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE_PI, ARG3 | ARG4 | ARG5 | ARG6, in main()
/external/strace/tests/
Dfutex.c90 ARG3 = 1 << 0, enumerator
132 if (((1 << i) == ARG3) || ((1 << i) == ARG6) || in invalid_op()
369 CHECK_INVALID_CLOCKRT(FUTEX_WAKE, ARG3, "%u"); in main()
406 CHECK_INVALID_CLOCKRT(FUTEX_WAKE_BITSET, ARG3 | ARG6, "%u", "%#x"); in main()
429 CHECK_INVALID_CLOCKRT(FUTEX_FD, ARG3, "%u"); in main()
463 CHECK_INVALID_CLOCKRT(FUTEX_REQUEUE, ARG3 | ARG4 | ARG5, "%u", "%u", in main()
511 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE, ARG3 | ARG4 | ARG5 | ARG6, in main()
624 CHECK_INVALID_CLOCKRT(FUTEX_WAKE_OP, ARG3 | ARG4 | ARG5 | ARG6, in main()
787 CHECK_INVALID_CLOCKRT(FUTEX_CMP_REQUEUE_PI, ARG3 | ARG4 | ARG5 | ARG6, in main()
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
Dtpu_parallel_execute_sink_resource_write.mlir79 …:%.+]]: tensor<i1>, [[ARG1:%.+]]: tensor<i1>, [[ARG2:%.+]]: tensor<i1>, [[ARG3:%.+]]: tensor<!tf.r…
83 // CHECK-NEXT: "tf.AssignVariableOp"([[ARG3]], [[ARG1]])
98 ….+]]: tensor<i1>, [[ARG1:%.+]]: tensor<i32>, [[ARG2:%.+]]: tensor<i64>, [[ARG3:%.+]]: tensor<f32>,…
103 // CHECK-NEXT: "tf.AssignVariableOp"([[ARG6]], [[ARG3]])
119 ….+]]: tensor<i1>, [[ARG1:%.+]]: tensor<i32>, [[ARG2:%.+]]: tensor<i64>, [[ARG3:%.+]]: tensor<bf16>…
129 // CHECK-NEXT: tf_device.return [[ARG3]], [[ARG5]] : tensor<bf16>, tensor<f64>
Dtpu_reorder_replicate_and_partitioned_inputs.mlir4 …nsor<10x3xf32>>>, [[ARG2:%.*]]: tensor<!tf.resource<tensor<10x3xf32>>>, [[ARG3:%.*]]: tensor<!tf.r…
7 // CHECK: [[RI_1:%.*]] = "tf.TPUReplicatedInput"([[ARG1]], [[ARG3]])
17 …nsor<10x3xf32>>>, [[ARG2:%.*]]: tensor<!tf.resource<tensor<10x3xf32>>>, [[ARG3:%.*]]: tensor<!tf.r…
20 // CHECK: [[RI_1:%.*]] = "tf.TPUReplicatedInput"([[ARG1]], [[ARG3]])
33 …nsor<10x3xf32>>>, [[ARG2:%.*]]: tensor<!tf.resource<tensor<10x3xf32>>>, [[ARG3:%.*]]: tensor<!tf.r…
37 // CHECK: [[PI_1:%.*]] = "tf.TPUPartitionedInput"([[ARG2]], [[ARG3]])
/external/llvm-project/mlir/test/Conversion/SPIRVToLLVM/
Dfunc-ops-to-llvm.mlir68 // CHECK-SAME: %[[ARG0:.*]]: !llvm.i32, %[[ARG1:.*]]: !llvm.i1, %[[ARG2:.*]]: !llvm.double, %[[ARG3…
71 // CHECK: llvm.call @void_2(%[[ARG3]]) : (!llvm.vec<2 x i64>) -> ()
73 …// CHECK: llvm.call @value_vector(%[[ARG3]], %[[ARG4]]) : (!llvm.vec<2 x i64>, !llvm.vec<2 x float…
/external/tensorflow/tensorflow/compiler/mlir/xla/tests/translate/
Dfusion.hlotxt7 // CHECK: ^bb0(%[[ARG2:.*]]: tensor<f32>, %[[ARG3:.*]]: tensor<f32>):
10 // CHECK: ^bb0(%[[ARG2:.*]]: tensor<f32>, %[[ARG3:.*]]: tensor<f32>):
/external/llvm-project/mlir/test/Dialect/SCF/
Dparallel-loop-tiling.mlir18 // CHECK-SAME: [[ARG1:%.*]]: index, [[ARG2:%.*]]: index, [[ARG3:%.*]]: index…
24 // CHECK: scf.parallel ([[V3:%.*]], [[V4:%.*]]) = ([[ARG1]], [[ARG2]]) to ([[ARG3]], [[AR…
25 // CHECK: [[V5:%.*]] = affine.min #map([[V1]], [[ARG3]], [[V3]])
/external/llvm-project/llvm/test/Transforms/GVN/
Dloadpre-missed-opportunity.ll25 ; PRE-NEXT: br i1 [[ARG3:%.*]], label [[BB16:%.*]], label [[BB15]]
55 ; CHECK-NEXT: br i1 [[ARG3:%.*]], label [[BB16:%.*]], label [[BB15]]

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