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Searched refs:ARM_AP_TZC_DRAM1_BASE (Results 1 – 8 of 8) sorted by relevance

/external/arm-trusted-firmware/include/plat/arm/common/
Darm_def.h97 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ macro
103 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
128 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \
425 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE
426 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
492 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
494 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
495 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
498 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
504 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \
[all …]
Dplat_arm.h44 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \
56 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \
/external/arm-trusted-firmware/plat/arm/board/rde1edge/
Drde1edge_security.c24 .region_base = ARM_AP_TZC_DRAM1_BASE,
25 .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
/external/arm-trusted-firmware/plat/arm/board/rdn1edge/
Drdn1edge_security.c24 .region_base = ARM_AP_TZC_DRAM1_BASE,
25 .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
/external/arm-trusted-firmware/plat/arm/board/sgi575/
Dsgi575_security.c25 .region_base = ARM_AP_TZC_DRAM1_BASE,
26 .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
/external/arm-trusted-firmware/plat/arm/board/juno/
Djuno_tzmp1_def.h16 #define JUNO_AP_TZC_SHARE_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
18 #define JUNO_AP_TZC_SHARE_DRAM1_END (ARM_AP_TZC_DRAM1_BASE - 1)
Djuno_security.c41 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},
/external/arm-trusted-firmware/plat/arm/board/tc0/include/
Dplatform_def.h32 #define TC0_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \