| /external/elfutils/libebl/ |
| D | eblcorenotetypename.c | 55 KNOWNSTYPE (ASRS), in ebl_core_note_type_name()
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 418 ASRS r7, r6, r5 // Must be wide - 3 distinct registers
419 ASRS r0, r0, r1 // Should choose narrow
420 ASRS r0, r1, r0 // Should choose wide - not commutative
421 ASRS.W r3, r3, r1 // Explicitly wide
422 ASRS.W r1, r1, r1
424 ASRS r7, r7, r1 // Should use narrow
425 ASRS r8, r1, r8 // high registers so must use wide encoding
426 ASRS r8, r8, r1
427 ASRS r5, r8, r5
428 ASRS r5, r5, r8
|
| /external/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 418 ASRS r7, r6, r5 // Must be wide - 3 distinct registers
419 ASRS r0, r0, r1 // Should choose narrow
420 ASRS r0, r1, r0 // Should choose wide - not commutative
421 ASRS.W r3, r3, r1 // Explicitly wide
422 ASRS.W r1, r1, r1
424 ASRS r7, r7, r1 // Should use narrow
425 ASRS r8, r1, r8 // high registers so must use wide encoding
426 ASRS r8, r8, r1
427 ASRS r5, r8, r5
428 ASRS r5, r5, r8
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-operand-rm-t32.json | 125 "Asrs", // ASRS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
126 // ASRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
|
| D | cond-rd-rn-operand-rm-a32.json | 75 "Asrs", // ASRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; A1
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_T2_32.c | 109 #define ASRS 0x4100 macro
857 return push_inst16(compiler, ASRS | RD3(dst) | RN3(arg2)); in emit_op_imm()
|
| /external/OpenCSD/decoder/tests/snapshots/TC2/ds5-dumps/ |
| D | ptmv1_0x13.txt | 212 Instruction 187 S:0xC004F59A 0x17F3 0 ASRS r3,r6,#31 false
335 Instruction 308 S:0xC004F59A 0x17F3 0 ASRS r3,r6,#31 false
1304 Instruction 1234 S:0xC0054F54 0x1149 0 ASRS r1,r1,#5 false
1354 Instruction 1282 S:0xC004F59A 0x17F3 0 ASRS r3,r6,#31 false
1717 Instruction 1641 S:0xC0043E74 0x17D3 0 ASRS r3,r2,#31 false
2043 Instruction 1962 S:0xC003FC5E 0x17DE 0 ASRS r6,r3,#31 false
2853 Instruction 2756 S:0xC004F59A 0x17F3 0 ASRS r3,r6,#31 false
2919 Instruction 2820 S:0xC0020588 0x17DB 0 ASRS r3,r3,#31 false
3061 Instruction 2952 S:0xC004F59A 0x17F3 0 ASRS r3,r6,#31 false
3672 Instruction 3557 S:0xC00352E4 0x17DF 0 ASRS r7,r3,#31 false
[all …]
|
| D | etmv3_0x11.txt | 460 Instruction 442 S:0xC004077A 0x1152 2 ASRS r2,r2,#5 false
480 Instruction 462 S:0xC00407B2 0x1140 1 ASRS r0,r0,#5 false
709 Instruction 684 S:0xC004098A 0x1140 1 ASRS r0,r0,#5 false
725 Instruction 700 S:0xC003D504 0x1149 2 ASRS r1,r1,#5 false
1012 Instruction 982 S:0xC0043E74 0x17D3 1 ASRS r3,r2,#31 false
1314 Instruction 1280 S:0xC003FC5E 0x17DE 1 ASRS r6,r3,#31 false
3302 Instruction 3230 S:0xC004F59A 0x17F3 1 ASRS r3,r6,#31 false
3490 Instruction 3412 S:0xC0020ECA 0x10B5 8 ASRS r5,r6,#2 false
3658 Instruction 3576 S:0xC0020ECA 0x10B5 1 ASRS r5,r6,#2 false
4405 Instruction 4278 S:0xC00456B2 0x1152 2 ASRS r2,r2,#5 false
[all …]
|
| D | etmv3_0x12.txt | 1463 Instruction 1427 S:0xC004F59A 0x17F3 1 ASRS r3,r6,#31 false
1652 Instruction 1609 S:0xC0020ECA 0x10B5 1 ASRS r5,r6,#2 false
1862 Instruction 1815 S:0xC0020ECA 0x10B5 8 ASRS r5,r6,#2 false
|
| D | etmv3_0x10.txt | 948 Instruction 887 S:0xC004F6EA 0x17DB 1 ASRS r3,r3,#31 false
1934 Instruction 1808 S:0xC003FC5E 0x17DE 1 ASRS r6,r3,#31 false
2294 Instruction 2162 S:0xC00422C2 0x17CE 1 ASRS r6,r1,#31 false
3360 Instruction 3178 S:0xC004F59A 0x17F3 1 ASRS r3,r6,#31 false
4968 Instruction 4750 S:0xC004F59A 0x17F3 1 ASRS r3,r6,#31 false
5156 Instruction 4932 S:0xC0020ECA 0x10B5 8 ASRS r5,r6,#2 false
5579 Instruction 5340 S:0xC0020ECA 0x10B5 8 ASRS r5,r6,#2 false
6373 Instruction 6084 S:0xC0020ECA 0x10B5 1 ASRS r5,r6,#2 false
6896 Instruction 6588 S:0xC0043E74 0x17D3 1 ASRS r3,r2,#31 false
7199 Instruction 6887 S:0xC003FC5E 0x17DE 1 ASRS r6,r3,#31 false
|