1 /*
2 * Copyright (C) 2018-2020 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8 /* CP110 Marvell SoC driver */
9
10 #include <common/debug.h>
11 #include <drivers/delay_timer.h>
12 #include <drivers/marvell/amb_adec.h>
13 #include <drivers/marvell/iob.h>
14 #include <drivers/marvell/mochi/cp110_setup.h>
15
16 #include <plat_marvell.h>
17
18 /*
19 * AXI Configuration.
20 */
21
22 /* Used for Units of CP-110 (e.g. USB device, USB Host, and etc) */
23 #define MVEBU_AXI_ATTR_OFFSET (0x441300)
24 #define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_OFFSET + \
25 0x4 * index)
26
27 /* AXI Protection bits */
28 #define MVEBU_AXI_PROT_OFFSET (0x441200)
29
30 /* AXI Protection regs */
31 #define MVEBU_AXI_PROT_REG(index) ((index <= 4) ? \
32 (MVEBU_AXI_PROT_OFFSET + \
33 0x4 * index) : \
34 (MVEBU_AXI_PROT_OFFSET + 0x18))
35 #define MVEBU_AXI_PROT_REGS_NUM (6)
36
37 #define MVEBU_SOC_CFGS_OFFSET (0x441900)
38 #define MVEBU_SOC_CFG_REG(index) (MVEBU_SOC_CFGS_OFFSET + \
39 0x4 * index)
40 #define MVEBU_SOC_CFG_REG_NUM (0)
41 #define MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK (0xE)
42
43 /* SATA3 MBUS to AXI regs */
44 #define MVEBU_BRIDGE_WIN_DIS_REG (MVEBU_SOC_CFGS_OFFSET + 0x10)
45 #define MVEBU_BRIDGE_WIN_DIS_OFF (0x0)
46
47 /* SATA3 MBUS to AXI regs */
48 #define MVEBU_SATA_M2A_AXI_PORT_CTRL_REG (0x54ff04)
49
50 /* AXI to MBUS bridge registers */
51 #define MVEBU_AMB_IP_OFFSET (0x13ff00)
52 #define MVEBU_AMB_IP_BRIDGE_WIN_REG(win) (MVEBU_AMB_IP_OFFSET + \
53 (win * 0x8))
54 #define MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET 0
55 #define MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK \
56 (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET)
57 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET 16
58 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK \
59 (0xffffu << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET)
60
61 #define MVEBU_SAMPLE_AT_RESET_REG (0x440600)
62 #define SAR_PCIE1_CLK_CFG_OFFSET 31
63 #define SAR_PCIE1_CLK_CFG_MASK (0x1u << SAR_PCIE1_CLK_CFG_OFFSET)
64 #define SAR_PCIE0_CLK_CFG_OFFSET 30
65 #define SAR_PCIE0_CLK_CFG_MASK (0x1 << SAR_PCIE0_CLK_CFG_OFFSET)
66 #define SAR_I2C_INIT_EN_OFFSET 24
67 #define SAR_I2C_INIT_EN_MASK (1 << SAR_I2C_INIT_EN_OFFSET)
68
69 /*******************************************************************************
70 * PCIE clock buffer control
71 ******************************************************************************/
72 #define MVEBU_PCIE_REF_CLK_BUF_CTRL (0x4404F0)
73 #define PCIE1_REFCLK_BUFF_SOURCE 0x800
74 #define PCIE0_REFCLK_BUFF_SOURCE 0x400
75
76 /*******************************************************************************
77 * MSS Device Push Set Register
78 ******************************************************************************/
79 #define MVEBU_CP_MSS_DPSHSR_REG (0x280040)
80 #define MSS_DPSHSR_REG_PCIE_CLK_SEL 0x8
81
82 /*******************************************************************************
83 * RTC Configuration
84 ******************************************************************************/
85 #define MVEBU_RTC_BASE (0x284000)
86 #define MVEBU_RTC_STATUS_REG (MVEBU_RTC_BASE + 0x0)
87 #define MVEBU_RTC_STATUS_ALARM1_MASK 0x1
88 #define MVEBU_RTC_STATUS_ALARM2_MASK 0x2
89 #define MVEBU_RTC_IRQ_1_CONFIG_REG (MVEBU_RTC_BASE + 0x4)
90 #define MVEBU_RTC_IRQ_2_CONFIG_REG (MVEBU_RTC_BASE + 0x8)
91 #define MVEBU_RTC_TIME_REG (MVEBU_RTC_BASE + 0xC)
92 #define MVEBU_RTC_ALARM_1_REG (MVEBU_RTC_BASE + 0x10)
93 #define MVEBU_RTC_ALARM_2_REG (MVEBU_RTC_BASE + 0x14)
94 #define MVEBU_RTC_CCR_REG (MVEBU_RTC_BASE + 0x18)
95 #define MVEBU_RTC_NOMINAL_TIMING 0x2000
96 #define MVEBU_RTC_NOMINAL_TIMING_MASK 0x7FFF
97 #define MVEBU_RTC_TEST_CONFIG_REG (MVEBU_RTC_BASE + 0x1C)
98 #define MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG (MVEBU_RTC_BASE + 0x80)
99 #define MVEBU_RTC_WRCLK_PERIOD_MASK 0xFFFF
100 #define MVEBU_RTC_WRCLK_PERIOD_DEFAULT 0x3FF
101 #define MVEBU_RTC_WRCLK_SETUP_OFFS 16
102 #define MVEBU_RTC_WRCLK_SETUP_MASK 0xFFFF0000
103 #define MVEBU_RTC_WRCLK_SETUP_DEFAULT 0x29
104 #define MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG (MVEBU_RTC_BASE + 0x84)
105 #define MVEBU_RTC_READ_OUTPUT_DELAY_MASK 0xFFFF
106 #define MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT 0x1F
107
108 enum axi_attr {
109 AXI_ADUNIT_ATTR = 0,
110 AXI_COMUNIT_ATTR,
111 AXI_EIP197_ATTR,
112 AXI_USB3D_ATTR,
113 AXI_USB3H0_ATTR,
114 AXI_USB3H1_ATTR,
115 AXI_SATA0_ATTR,
116 AXI_SATA1_ATTR,
117 AXI_DAP_ATTR,
118 AXI_DFX_ATTR,
119 AXI_DBG_TRC_ATTR = 12,
120 AXI_SDIO_ATTR,
121 AXI_MSS_ATTR,
122 AXI_MAX_ATTR,
123 };
124
125 /* Most stream IDS are configured centrally in the CP-110 RFU
126 * but some are configured inside the unit registers
127 */
128 #define RFU_STREAM_ID_BASE (0x450000)
129 #define USB3H_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0xC)
130 #define USB3H_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x10)
131 #define SATA_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x14)
132 #define SATA_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x18)
133 #define SDIO_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x28)
134
135 #define CP_DMA_0_STREAM_ID_REG (0x6B0010)
136 #define CP_DMA_1_STREAM_ID_REG (0x6D0010)
137
138 /* We allocate IDs 128-255 for PCIe */
139 #define MAX_STREAM_ID (0x80)
140
141 uintptr_t stream_id_reg[] = {
142 USB3H_0_STREAM_ID_REG,
143 USB3H_1_STREAM_ID_REG,
144 CP_DMA_0_STREAM_ID_REG,
145 CP_DMA_1_STREAM_ID_REG,
146 SATA_0_STREAM_ID_REG,
147 SATA_1_STREAM_ID_REG,
148 SDIO_0_STREAM_ID_REG,
149 0
150 };
151
cp110_errata_wa_init(uintptr_t base)152 static void cp110_errata_wa_init(uintptr_t base)
153 {
154 uint32_t data;
155
156 /* ERRATA GL-4076863:
157 * Reset value for global_secure_enable inputs must be changed
158 * from '1' to '0'.
159 * When asserted, only "secured" transactions can enter IHB
160 * configuration space.
161 * However, blocking AXI transactions is performed by IOB.
162 * Performing it also at IHB/HB complicates programming model.
163 *
164 * Enable non-secure access in SOC configuration register
165 */
166 data = mmio_read_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM));
167 data &= ~MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK;
168 mmio_write_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM), data);
169 }
170
cp110_pcie_clk_cfg(uintptr_t base)171 static void cp110_pcie_clk_cfg(uintptr_t base)
172 {
173 uint32_t pcie0_clk, pcie1_clk, reg;
174
175 /*
176 * Determine the pcie0/1 clock direction (input/output) from the
177 * sample at reset.
178 */
179 reg = mmio_read_32(base + MVEBU_SAMPLE_AT_RESET_REG);
180 pcie0_clk = (reg & SAR_PCIE0_CLK_CFG_MASK) >> SAR_PCIE0_CLK_CFG_OFFSET;
181 pcie1_clk = (reg & SAR_PCIE1_CLK_CFG_MASK) >> SAR_PCIE1_CLK_CFG_OFFSET;
182
183 /* CP110 revision A2 */
184 if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2) {
185 /*
186 * PCIe Reference Clock Buffer Control register must be
187 * set according to the clock direction (input/output)
188 */
189 reg = mmio_read_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL);
190 reg &= ~(PCIE0_REFCLK_BUFF_SOURCE | PCIE1_REFCLK_BUFF_SOURCE);
191 if (!pcie0_clk)
192 reg |= PCIE0_REFCLK_BUFF_SOURCE;
193 if (!pcie1_clk)
194 reg |= PCIE1_REFCLK_BUFF_SOURCE;
195
196 mmio_write_32(base + MVEBU_PCIE_REF_CLK_BUF_CTRL, reg);
197 }
198
199 /* CP110 revision A1 */
200 if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A1) {
201 if (!pcie0_clk || !pcie1_clk) {
202 /*
203 * if one of the pcie clocks is set to input,
204 * we need to set mss_push[131] field, otherwise,
205 * the pcie clock might not work.
206 */
207 reg = mmio_read_32(base + MVEBU_CP_MSS_DPSHSR_REG);
208 reg |= MSS_DPSHSR_REG_PCIE_CLK_SEL;
209 mmio_write_32(base + MVEBU_CP_MSS_DPSHSR_REG, reg);
210 }
211 }
212 }
213
214 /* Set a unique stream id for all DMA capable devices */
cp110_stream_id_init(uintptr_t base,uint32_t stream_id)215 static void cp110_stream_id_init(uintptr_t base, uint32_t stream_id)
216 {
217 int i = 0;
218
219 while (stream_id_reg[i]) {
220 if (i > MAX_STREAM_ID_PER_CP) {
221 NOTICE("Only first %d (maximum) Stream IDs allocated\n",
222 MAX_STREAM_ID_PER_CP);
223 return;
224 }
225
226 if ((stream_id_reg[i] == CP_DMA_0_STREAM_ID_REG) ||
227 (stream_id_reg[i] == CP_DMA_1_STREAM_ID_REG))
228 mmio_write_32(base + stream_id_reg[i],
229 stream_id << 16 | stream_id);
230 else
231 mmio_write_32(base + stream_id_reg[i], stream_id);
232
233 /* SATA port 0/1 are in the same SATA unit, and they should use
234 * the same STREAM ID number
235 */
236 if (stream_id_reg[i] != SATA_0_STREAM_ID_REG)
237 stream_id++;
238
239 i++;
240 }
241 }
242
cp110_axi_attr_init(uintptr_t base)243 static void cp110_axi_attr_init(uintptr_t base)
244 {
245 uint32_t index, data;
246
247 /* Initialize AXI attributes for Armada-7K/8K SoC */
248
249 /* Go over the AXI attributes and set Ax-Cache and Ax-Domain */
250 for (index = 0; index < AXI_MAX_ATTR; index++) {
251 switch (index) {
252 /* DFX and MSS unit works with no coherent only -
253 * there's no option to configure the Ax-Cache and Ax-Domain
254 */
255 case AXI_DFX_ATTR:
256 case AXI_MSS_ATTR:
257 continue;
258 default:
259 /* Set Ax-Cache as cacheable, no allocate, modifiable,
260 * bufferable
261 * The values are different because Read & Write
262 * definition is different in Ax-Cache
263 */
264 data = mmio_read_32(base + MVEBU_AXI_ATTR_REG(index));
265 data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK;
266 data |= (CACHE_ATTR_WRITE_ALLOC |
267 CACHE_ATTR_CACHEABLE |
268 CACHE_ATTR_BUFFERABLE) <<
269 MVEBU_AXI_ATTR_ARCACHE_OFFSET;
270 data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK;
271 data |= (CACHE_ATTR_READ_ALLOC |
272 CACHE_ATTR_CACHEABLE |
273 CACHE_ATTR_BUFFERABLE) <<
274 MVEBU_AXI_ATTR_AWCACHE_OFFSET;
275 /* Set Ax-Domain as Outer domain */
276 data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK;
277 data |= DOMAIN_OUTER_SHAREABLE <<
278 MVEBU_AXI_ATTR_ARDOMAIN_OFFSET;
279 data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK;
280 data |= DOMAIN_OUTER_SHAREABLE <<
281 MVEBU_AXI_ATTR_AWDOMAIN_OFFSET;
282 mmio_write_32(base + MVEBU_AXI_ATTR_REG(index), data);
283 }
284 }
285
286 /* SATA IOCC supported, cache attributes
287 * for SATA MBUS to AXI configuration.
288 */
289 data = mmio_read_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG);
290 data &= ~MVEBU_SATA_M2A_AXI_AWCACHE_MASK;
291 data |= (CACHE_ATTR_WRITE_ALLOC |
292 CACHE_ATTR_CACHEABLE |
293 CACHE_ATTR_BUFFERABLE) <<
294 MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET;
295 data &= ~MVEBU_SATA_M2A_AXI_ARCACHE_MASK;
296 data |= (CACHE_ATTR_READ_ALLOC |
297 CACHE_ATTR_CACHEABLE |
298 CACHE_ATTR_BUFFERABLE) <<
299 MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET;
300 mmio_write_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG, data);
301
302 /* Set all IO's AXI attribute to non-secure access. */
303 for (index = 0; index < MVEBU_AXI_PROT_REGS_NUM; index++)
304 mmio_write_32(base + MVEBU_AXI_PROT_REG(index),
305 DOMAIN_SYSTEM_SHAREABLE);
306 }
307
cp110_amb_init(uintptr_t base)308 void cp110_amb_init(uintptr_t base)
309 {
310 uint32_t reg;
311
312 /* Open AMB bridge Window to Access COMPHY/MDIO registers */
313 reg = mmio_read_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0));
314 reg &= ~(MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK |
315 MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK);
316 reg |= (0x7ff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET) |
317 (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET);
318 mmio_write_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0), reg);
319 }
320
cp110_rtc_init(uintptr_t base)321 static void cp110_rtc_init(uintptr_t base)
322 {
323 /* Update MBus timing parameters before accessing RTC registers */
324 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG,
325 MVEBU_RTC_WRCLK_PERIOD_MASK,
326 MVEBU_RTC_WRCLK_PERIOD_DEFAULT);
327
328 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG,
329 MVEBU_RTC_WRCLK_SETUP_MASK,
330 MVEBU_RTC_WRCLK_SETUP_DEFAULT <<
331 MVEBU_RTC_WRCLK_SETUP_OFFS);
332
333 mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG,
334 MVEBU_RTC_READ_OUTPUT_DELAY_MASK,
335 MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT);
336
337 /*
338 * Issue reset to the RTC if Clock Correction register
339 * contents did not sustain the reboot/power-on.
340 */
341 if ((mmio_read_32(base + MVEBU_RTC_CCR_REG) &
342 MVEBU_RTC_NOMINAL_TIMING_MASK) != MVEBU_RTC_NOMINAL_TIMING) {
343 /* Reset Test register */
344 mmio_write_32(base + MVEBU_RTC_TEST_CONFIG_REG, 0);
345 mdelay(500);
346
347 /* Reset Status register */
348 mmio_write_32(base + MVEBU_RTC_STATUS_REG,
349 (MVEBU_RTC_STATUS_ALARM1_MASK |
350 MVEBU_RTC_STATUS_ALARM2_MASK));
351 udelay(62);
352
353 /* Turn off Int1 and Int2 sources & clear the Alarm count */
354 mmio_write_32(base + MVEBU_RTC_IRQ_1_CONFIG_REG, 0);
355 mmio_write_32(base + MVEBU_RTC_IRQ_2_CONFIG_REG, 0);
356 mmio_write_32(base + MVEBU_RTC_ALARM_1_REG, 0);
357 mmio_write_32(base + MVEBU_RTC_ALARM_2_REG, 0);
358
359 /* Setup nominal register access timing */
360 mmio_write_32(base + MVEBU_RTC_CCR_REG,
361 MVEBU_RTC_NOMINAL_TIMING);
362
363 /* Reset Status register */
364 mmio_write_32(base + MVEBU_RTC_STATUS_REG,
365 (MVEBU_RTC_STATUS_ALARM1_MASK |
366 MVEBU_RTC_STATUS_ALARM2_MASK));
367 udelay(50);
368 }
369 }
370
cp110_amb_adec_init(uintptr_t base)371 static void cp110_amb_adec_init(uintptr_t base)
372 {
373 /* enable AXI-MBUS by clearing "Bridge Windows Disable" */
374 mmio_clrbits_32(base + MVEBU_BRIDGE_WIN_DIS_REG,
375 (1 << MVEBU_BRIDGE_WIN_DIS_OFF));
376
377 /* configure AXI-MBUS windows for CP */
378 init_amb_adec(base);
379 }
380
cp110_init(uintptr_t cp110_base,uint32_t stream_id)381 void cp110_init(uintptr_t cp110_base, uint32_t stream_id)
382 {
383 INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base);
384
385 /* configure IOB windows for CP0*/
386 init_iob(cp110_base);
387
388 /* configure AXI-MBUS windows for CP0*/
389 cp110_amb_adec_init(cp110_base);
390
391 /* configure axi for CP0*/
392 cp110_axi_attr_init(cp110_base);
393
394 /* Execute SW WA for erratas */
395 cp110_errata_wa_init(cp110_base);
396
397 /* Confiure pcie clock according to clock direction */
398 cp110_pcie_clk_cfg(cp110_base);
399
400 /* configure stream id for CP0 */
401 cp110_stream_id_init(cp110_base, stream_id);
402
403 /* Open AMB bridge for comphy for CP0 & CP1*/
404 cp110_amb_init(cp110_base);
405
406 /* Reset RTC if needed */
407 cp110_rtc_init(cp110_base);
408 }
409
410 /* Do the minimal setup required to configure the CP in BLE */
cp110_ble_init(uintptr_t cp110_base)411 void cp110_ble_init(uintptr_t cp110_base)
412 {
413 #if PCI_EP_SUPPORT
414 INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base);
415
416 cp110_amb_init(cp110_base);
417
418 /* Configure PCIe clock */
419 cp110_pcie_clk_cfg(cp110_base);
420
421 /* Configure PCIe endpoint */
422 ble_plat_pcie_ep_setup();
423 #endif
424 }
425