1 /* 2 * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef AXI_REGISTERS_H 8 #define AXI_REGISTERS_H 9 10 /* AXI registers */ 11 12 /* AXI base address */ 13 #define AXI_BASE (0xE6780000U) 14 15 /* address split */ 16 17 /* AXI address split control 0 */ 18 #define AXI_ADSPLCR0 (AXI_BASE + 0x4008U) 19 /* AXI address split control 1 */ 20 #define AXI_ADSPLCR1 (AXI_BASE + 0x400CU) 21 /* AXI address split control 2 */ 22 #define AXI_ADSPLCR2 (AXI_BASE + 0x4010U) 23 /* AXI address split control 3 */ 24 #define AXI_ADSPLCR3 (AXI_BASE + 0x4014U) 25 26 /* functional safety */ 27 28 /* AXI functional safety control */ 29 #define AXI_FUSACR (AXI_BASE + 0x4020U) 30 31 /* decompression */ 32 33 /* AXI decompression area configuration A0 */ 34 #define AXI_DCMPAREACRA0 (AXI_BASE + 0x4100U) 35 /* AXI decompression area configuration B0 */ 36 #define AXI_DCMPAREACRB0 (AXI_BASE + 0x4104U) 37 /* AXI decompression area configuration A1 */ 38 #define AXI_DCMPAREACRA1 (AXI_BASE + 0x4108U) 39 /* AXI decompression area configuration B1 */ 40 #define AXI_DCMPAREACRB1 (AXI_BASE + 0x410CU) 41 /* AXI decompression area configuration A2 */ 42 #define AXI_DCMPAREACRA2 (AXI_BASE + 0x4110U) 43 /* AXI decompression area configuration B2 */ 44 #define AXI_DCMPAREACRB2 (AXI_BASE + 0x4114U) 45 /* AXI decompression area configuration A3 */ 46 #define AXI_DCMPAREACRA3 (AXI_BASE + 0x4118U) 47 /* AXI decompression area configuration B3 */ 48 #define AXI_DCMPAREACRB3 (AXI_BASE + 0x411CU) 49 /* AXI decompression area configuration A4 */ 50 #define AXI_DCMPAREACRA4 (AXI_BASE + 0x4120U) 51 /* AXI decompression area configuration B4 */ 52 #define AXI_DCMPAREACRB4 (AXI_BASE + 0x4124U) 53 /* AXI decompression area configuration A5 */ 54 #define AXI_DCMPAREACRA5 (AXI_BASE + 0x4128U) 55 /* AXI decompression area configuration B5 */ 56 #define AXI_DCMPAREACRB5 (AXI_BASE + 0x412CU) 57 /* AXI decompression area configuration A6 */ 58 #define AXI_DCMPAREACRA6 (AXI_BASE + 0x4130U) 59 /* AXI decompression area configuration B6 */ 60 #define AXI_DCMPAREACRB6 (AXI_BASE + 0x4134U) 61 /* AXI decompression area configuration A7 */ 62 #define AXI_DCMPAREACRA7 (AXI_BASE + 0x4138U) 63 /* AXI decompression area configuration B7 */ 64 #define AXI_DCMPAREACRB7 (AXI_BASE + 0x413CU) 65 /* AXI decompression area configuration A8 */ 66 #define AXI_DCMPAREACRA8 (AXI_BASE + 0x4140U) 67 /* AXI decompression area configuration B8 */ 68 #define AXI_DCMPAREACRB8 (AXI_BASE + 0x4144U) 69 /* AXI decompression area configuration A9 */ 70 #define AXI_DCMPAREACRA9 (AXI_BASE + 0x4148U) 71 /* AXI decompression area configuration B9 */ 72 #define AXI_DCMPAREACRB9 (AXI_BASE + 0x414CU) 73 /* AXI decompression area configuration A10 */ 74 #define AXI_DCMPAREACRA10 (AXI_BASE + 0x4150U) 75 /* AXI decompression area configuration B10 */ 76 #define AXI_DCMPAREACRB10 (AXI_BASE + 0x4154U) 77 /* AXI decompression area configuration A11 */ 78 #define AXI_DCMPAREACRA11 (AXI_BASE + 0x4158U) 79 /* AXI decompression area configuration B11 */ 80 #define AXI_DCMPAREACRB11 (AXI_BASE + 0x415CU) 81 /* AXI decompression area configuration A12 */ 82 #define AXI_DCMPAREACRA12 (AXI_BASE + 0x4160U) 83 /* AXI decompression area configuration B12 */ 84 #define AXI_DCMPAREACRB12 (AXI_BASE + 0x4164U) 85 /* AXI decompression area configuration A13 */ 86 #define AXI_DCMPAREACRA13 (AXI_BASE + 0x4168U) 87 /* AXI decompression area configuration B13 */ 88 #define AXI_DCMPAREACRB13 (AXI_BASE + 0x416CU) 89 /* AXI decompression area configuration A14 */ 90 #define AXI_DCMPAREACRA14 (AXI_BASE + 0x4170U) 91 /* AXI decompression area configuration B14 */ 92 #define AXI_DCMPAREACRB14 (AXI_BASE + 0x4174U) 93 /* AXI decompression area configuration A15 */ 94 #define AXI_DCMPAREACRA15 (AXI_BASE + 0x4178U) 95 /* AXI decompression area configuration B15 */ 96 #define AXI_DCMPAREACRB15 (AXI_BASE + 0x417CU) 97 /* AXI decompression shadow area configuration */ 98 #define AXI_DCMPSHDWCR (AXI_BASE + 0x4280U) 99 100 /* SDRAM protection */ 101 102 /* AXI dram protected area division 0 */ 103 #define AXI_DPTDIVCR0 (AXI_BASE + 0x4400U) 104 /* AXI dram protected area division 1 */ 105 #define AXI_DPTDIVCR1 (AXI_BASE + 0x4404U) 106 /* AXI dram protected area division 2 */ 107 #define AXI_DPTDIVCR2 (AXI_BASE + 0x4408U) 108 /* AXI dram protected area division 3 */ 109 #define AXI_DPTDIVCR3 (AXI_BASE + 0x440CU) 110 /* AXI dram protected area division 4 */ 111 #define AXI_DPTDIVCR4 (AXI_BASE + 0x4410U) 112 /* AXI dram protected area division 5 */ 113 #define AXI_DPTDIVCR5 (AXI_BASE + 0x4414U) 114 /* AXI dram protected area division 6 */ 115 #define AXI_DPTDIVCR6 (AXI_BASE + 0x4418U) 116 /* AXI dram protected area division 7 */ 117 #define AXI_DPTDIVCR7 (AXI_BASE + 0x441CU) 118 /* AXI dram protected area division 8 */ 119 #define AXI_DPTDIVCR8 (AXI_BASE + 0x4420U) 120 /* AXI dram protected area division 9 */ 121 #define AXI_DPTDIVCR9 (AXI_BASE + 0x4424U) 122 /* AXI dram protected area division 10 */ 123 #define AXI_DPTDIVCR10 (AXI_BASE + 0x4428U) 124 /* AXI dram protected area division 11 */ 125 #define AXI_DPTDIVCR11 (AXI_BASE + 0x442CU) 126 /* AXI dram protected area division 12 */ 127 #define AXI_DPTDIVCR12 (AXI_BASE + 0x4430U) 128 /* AXI dram protected area division 13 */ 129 #define AXI_DPTDIVCR13 (AXI_BASE + 0x4434U) 130 /* AXI dram protected area division 14 */ 131 #define AXI_DPTDIVCR14 (AXI_BASE + 0x4438U) 132 133 /* AXI dram protected area setting 0 */ 134 #define AXI_DPTCR0 (AXI_BASE + 0x4440U) 135 /* AXI dram protected area setting 1 */ 136 #define AXI_DPTCR1 (AXI_BASE + 0x4444U) 137 /* AXI dram protected area setting 2 */ 138 #define AXI_DPTCR2 (AXI_BASE + 0x4448U) 139 /* AXI dram protected area setting 3 */ 140 #define AXI_DPTCR3 (AXI_BASE + 0x444CU) 141 /* AXI dram protected area setting 4 */ 142 #define AXI_DPTCR4 (AXI_BASE + 0x4450U) 143 /* AXI dram protected area setting 5 */ 144 #define AXI_DPTCR5 (AXI_BASE + 0x4454U) 145 /* AXI dram protected area setting 6 */ 146 #define AXI_DPTCR6 (AXI_BASE + 0x4458U) 147 /* AXI dram protected area setting 7 */ 148 #define AXI_DPTCR7 (AXI_BASE + 0x445CU) 149 /* AXI dram protected area setting 8 */ 150 #define AXI_DPTCR8 (AXI_BASE + 0x4460U) 151 /* AXI dram protected area setting 9 */ 152 #define AXI_DPTCR9 (AXI_BASE + 0x4464U) 153 /* AXI dram protected area setting 10 */ 154 #define AXI_DPTCR10 (AXI_BASE + 0x4468U) 155 /* AXI dram protected area setting 11 */ 156 #define AXI_DPTCR11 (AXI_BASE + 0x446CU) 157 /* AXI dram protected area setting 12 */ 158 #define AXI_DPTCR12 (AXI_BASE + 0x4470U) 159 /* AXI dram protected area setting 13 */ 160 #define AXI_DPTCR13 (AXI_BASE + 0x4474U) 161 /* AXI dram protected area setting 14 */ 162 #define AXI_DPTCR14 (AXI_BASE + 0x4478U) 163 /* AXI dram protected area setting 15 */ 164 #define AXI_DPTCR15 (AXI_BASE + 0x447CU) 165 166 /* SRAM protection */ 167 168 /* AXI sram protected area division 0 */ 169 #define AXI_SPTDIVCR0 (AXI_BASE + 0x4500U) 170 /* AXI sram protected area division 1 */ 171 #define AXI_SPTDIVCR1 (AXI_BASE + 0x4504U) 172 /* AXI sram protected area division 2 */ 173 #define AXI_SPTDIVCR2 (AXI_BASE + 0x4508U) 174 /* AXI sram protected area division 3 */ 175 #define AXI_SPTDIVCR3 (AXI_BASE + 0x450CU) 176 /* AXI sram protected area division 4 */ 177 #define AXI_SPTDIVCR4 (AXI_BASE + 0x4510U) 178 /* AXI sram protected area division 5 */ 179 #define AXI_SPTDIVCR5 (AXI_BASE + 0x4514U) 180 /* AXI sram protected area division 6 */ 181 #define AXI_SPTDIVCR6 (AXI_BASE + 0x4518U) 182 /* AXI sram protected area division 7 */ 183 #define AXI_SPTDIVCR7 (AXI_BASE + 0x451CU) 184 /* AXI sram protected area division 8 */ 185 #define AXI_SPTDIVCR8 (AXI_BASE + 0x4520U) 186 /* AXI sram protected area division 9 */ 187 #define AXI_SPTDIVCR9 (AXI_BASE + 0x4524U) 188 /* AXI sram protected area division 10 */ 189 #define AXI_SPTDIVCR10 (AXI_BASE + 0x4528U) 190 /* AXI sram protected area division 11 */ 191 #define AXI_SPTDIVCR11 (AXI_BASE + 0x452CU) 192 /* AXI sram protected area division 12 */ 193 #define AXI_SPTDIVCR12 (AXI_BASE + 0x4530U) 194 /* AXI sram protected area division 13 */ 195 #define AXI_SPTDIVCR13 (AXI_BASE + 0x4534U) 196 /* AXI sram protected area division 14 */ 197 #define AXI_SPTDIVCR14 (AXI_BASE + 0x4538U) 198 199 /* AXI sram protected area setting 0 */ 200 #define AXI_SPTCR0 (AXI_BASE + 0x4540U) 201 /* AXI sram protected area setting 1 */ 202 #define AXI_SPTCR1 (AXI_BASE + 0x4544U) 203 /* AXI sram protected area setting 2 */ 204 #define AXI_SPTCR2 (AXI_BASE + 0x4548U) 205 /* AXI sram protected area setting 3 */ 206 #define AXI_SPTCR3 (AXI_BASE + 0x454CU) 207 /* AXI sram protected area setting 4 */ 208 #define AXI_SPTCR4 (AXI_BASE + 0x4550U) 209 /* AXI sram protected area setting 5 */ 210 #define AXI_SPTCR5 (AXI_BASE + 0x4554U) 211 /* AXI sram protected area setting 6 */ 212 #define AXI_SPTCR6 (AXI_BASE + 0x4558U) 213 /* AXI sram protected area setting 7 */ 214 #define AXI_SPTCR7 (AXI_BASE + 0x455CU) 215 /* AXI sram protected area setting 8 */ 216 #define AXI_SPTCR8 (AXI_BASE + 0x4560U) 217 /* AXI sram protected area setting 9 */ 218 #define AXI_SPTCR9 (AXI_BASE + 0x4564U) 219 /* AXI sram protected area setting 10 */ 220 #define AXI_SPTCR10 (AXI_BASE + 0x4568U) 221 /* AXI sram protected area setting 11 */ 222 #define AXI_SPTCR11 (AXI_BASE + 0x456CU) 223 /* AXI sram protected area setting 12 */ 224 #define AXI_SPTCR12 (AXI_BASE + 0x4570U) 225 /* AXI sram protected area setting 13 */ 226 #define AXI_SPTCR13 (AXI_BASE + 0x4574U) 227 /* AXI sram protected area setting 14 */ 228 #define AXI_SPTCR14 (AXI_BASE + 0x4578U) 229 /* AXI sram protected area setting 15 */ 230 #define AXI_SPTCR15 (AXI_BASE + 0x457CU) 231 232 /* EDC base address */ 233 #define EDC_BASE (0xFF840000U) 234 235 /* EDC edc enable */ 236 #define EDC_EDCEN (EDC_BASE + 0x0010U) 237 /* EDC edc status 0 */ 238 #define EDC_EDCST0 (EDC_BASE + 0x0020U) 239 /* EDC edc status 1 */ 240 #define EDC_EDCST1 (EDC_BASE + 0x0024U) 241 /* EDC edc interrupt enable 0 */ 242 #define EDC_EDCINTEN0 (EDC_BASE + 0x0040U) 243 /* EDC edc interrupt enable 1 */ 244 #define EDC_EDCINTEN1 (EDC_BASE + 0x0044U) 245 246 #endif /* AXI_REGISTERS_H */ 247