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Searched refs:AlignSize (Results 1 – 6 of 6) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp192 int AlignSize) { in smallData() argument
199 if (AlignSize == 8) { in smallData()
221 OutStreamer.EmitIntValue(Value, AlignSize); in smallData()
222 OutStreamer.EmitCodeAlignment(AlignSize); in smallData()
249 OutStreamer.EmitValue(Imm.getExpr(), AlignSize); in smallData()
250 OutStreamer.EmitCodeAlignment(AlignSize); in smallData()
DHexagonInstrInfo.td3662 MemAccessSize AlignSize, string RegSrc = "Rt">
3672 let accessSize = AlignSize;
3684 !if (!eq(!cast<string>(AlignSize), "DoubleWordAccess"), offset{6-3},
3685 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3686 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3704 bits<2>MajOp, MemAccessSize AlignSize>
3715 let accessSize = AlignSize;
3725 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
3726 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
3740 MemAccessSize AlignSize, string RegSrc = "Rt">
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp182 int AlignSize) { in smallData() argument
189 if (AlignSize == 8) { in smallData()
211 OutStreamer.EmitIntValue(Value, AlignSize); in smallData()
212 OutStreamer.EmitCodeAlignment(AlignSize); in smallData()
239 OutStreamer.EmitValue(Imm.getExpr(), AlignSize); in smallData()
240 OutStreamer.EmitCodeAlignment(AlignSize); in smallData()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp182 int AlignSize) { in smallData() argument
189 if (AlignSize == 8) { in smallData()
211 OutStreamer.emitIntValue(Value, AlignSize); in smallData()
212 OutStreamer.emitCodeAlignment(AlignSize); in smallData()
239 OutStreamer.emitValue(Imm.getExpr(), AlignSize); in smallData()
240 OutStreamer.emitCodeAlignment(AlignSize); in smallData()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp2119 unsigned AlignSize = 1; in getRegularReg() local
2123 AlignSize = std::min(RegWidth, 4u); in getRegularReg()
2126 if (RegNum % AlignSize != 0) in getRegularReg()
2129 unsigned RegIdx = RegNum / AlignSize; in getRegularReg()
/external/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp2273 unsigned AlignSize = 1; in getRegularReg() local
2277 AlignSize = std::min(RegWidth, 4u); in getRegularReg()
2280 if (RegNum % AlignSize != 0) { in getRegularReg()
2285 unsigned RegIdx = RegNum / AlignSize; in getRegularReg()