Home
last modified time | relevance | path

Searched refs:AlignedAddr (Results 1 – 24 of 24) sorted by relevance

/external/clang/test/CodeGen/
Darm-vector-align.c14 typedef float AlignedAddr __attribute__ ((aligned (16))); typedef
15 void t1(AlignedAddr *addr1, AlignedAddr *addr2) { in t1()
/external/llvm-project/clang/test/CodeGen/
Darm-vector-align.c14 typedef float AlignedAddr __attribute__ ((aligned (16))); typedef
15 void t1(AlignedAddr *addr1, AlignedAddr *addr2) { in t1()
/external/llvm/test/Transforms/AtomicExpand/SPARC/
Dpartword.ll15 ; CHECK: %AlignedAddr = inttoptr i64 %1 to i32*
26 ; CHECK: %8 = load i32, i32* %AlignedAddr
33 ; CHECK: %13 = cmpxchg i32* %AlignedAddr, i32 %12, i32 %11 monotonic monotonic
60 ; CHECK: %AlignedAddr = inttoptr i64 %1 to i32*
71 ; CHECK: %8 = load i32, i32* %AlignedAddr
78 ; CHECK: %13 = cmpxchg i32* %AlignedAddr, i32 %12, i32 %11 monotonic monotonic
106 ; CHECK: %AlignedAddr = inttoptr i64 %1 to i32*
115 ; CHECK: %5 = load i32, i32* %AlignedAddr, align 4
123 ; CHECK: %9 = cmpxchg i32* %AlignedAddr, i32 %loaded, i32 %8 monotonic monotonic
142 ; CHECK: %6 = cmpxchg i32* %AlignedAddr, i32 %loaded, i32 %new monotonic monotonic
[all …]
/external/llvm-project/llvm/test/Transforms/AtomicExpand/SPARC/
Dpartword.ll15 ; CHECK: %AlignedAddr = inttoptr i64 %1 to i32*
26 ; CHECK: %8 = load i32, i32* %AlignedAddr
33 ; CHECK: %13 = cmpxchg i32* %AlignedAddr, i32 %12, i32 %11 monotonic monotonic
60 ; CHECK: %AlignedAddr = inttoptr i64 %1 to i32*
71 ; CHECK: %8 = load i32, i32* %AlignedAddr
78 ; CHECK: %13 = cmpxchg i32* %AlignedAddr, i32 %12, i32 %11 monotonic monotonic
106 ; CHECK: %AlignedAddr = inttoptr i64 %1 to i32*
115 ; CHECK: %5 = load i32, i32* %AlignedAddr, align 4
123 ; CHECK: %9 = cmpxchg i32* %AlignedAddr, i32 %loaded, i32 %8 monotonic monotonic
142 ; CHECK: %6 = cmpxchg i32* %AlignedAddr, i32 %loaded, i32 %new monotonic monotonic
[all …]
/external/llvm/include/llvm/Support/
DAllocator.h240 uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment); in Allocate() local
241 assert(AlignedAddr + Size <= (uintptr_t)NewSlab + PaddedSize); in Allocate()
242 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
250 uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment); in Allocate() local
251 assert(AlignedAddr + Size <= (uintptr_t)End && in Allocate()
253 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
/external/swiftshader/third_party/llvm-subzero/include/llvm/Support/
DAllocator.h243 uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment); in Allocate() local
244 assert(AlignedAddr + Size <= (uintptr_t)NewSlab + PaddedSize); in Allocate()
245 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
253 uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment); in Allocate() local
254 assert(AlignedAddr + Size <= (uintptr_t)End && in Allocate()
256 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
/external/llvm-project/llvm/include/llvm/Support/
DAllocator.h179 uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment); in Allocate() local
180 assert(AlignedAddr + Size <= (uintptr_t)NewSlab + PaddedSize); in Allocate()
181 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
189 uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment); in Allocate() local
190 assert(AlignedAddr + SizeToAllocate <= (uintptr_t)End && in Allocate()
192 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DAllocator.h250 uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment); in Allocate() local
251 assert(AlignedAddr + Size <= (uintptr_t)NewSlab + PaddedSize); in Allocate()
252 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
260 uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment); in Allocate() local
261 assert(AlignedAddr + SizeToAllocate <= (uintptr_t)End && in Allocate()
263 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
/external/llvm-project/clang/test/Analysis/inlining/
Dplacement-new-fp-suppression.cpp57 uintptr_t AlignedAddr = alignAddr(Allocator.Allocate(PaddedSize, 0), in Allocate() local
59 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
/external/llvm-project/llvm/lib/CodeGen/
DAtomicExpandPass.cpp583 Value *AlignedAddr = nullptr; member
605 PrintObj(PMV.AlignedAddr); in operator <<()
648 PMV.AlignedAddr = Addr; in createMaskInstrs()
658 PMV.AlignedAddr = Builder.CreateIntToPtr( in createMaskInstrs()
782 insertRMWCmpXchgLoop(Builder, PMV.WordType, PMV.AlignedAddr, MemOpOrder, in expandPartwordAtomicRMW()
786 OldResult = insertRMWLLSCLoop(Builder, PMV.WordType, PMV.AlignedAddr, in expandPartwordAtomicRMW()
820 AtomicRMWInst *NewAI = Builder.CreateAtomicRMW(Op, PMV.AlignedAddr, in widenPartwordAtomicRMW()
898 LoadInst *InitLoaded = Builder.CreateLoad(PMV.WordType, PMV.AlignedAddr); in expandPartwordCmpXchg()
912 PMV.AlignedAddr, FullWord_Cmp, FullWord_NewVal, CI->getSuccessOrdering(), in expandPartwordCmpXchg()
985 Builder, AI, PMV.AlignedAddr, ValOperand_Shifted, PMV.Mask, PMV.ShiftAmt, in expandAtomicRMWToMaskedIntrinsic()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVISelLowering.h211 IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
217 Value *AlignedAddr, Value *CmpVal,
DRISCVISelLowering.cpp2813 IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, in emitMaskedAtomicRMWIntrinsic() argument
2818 Type *Tys[] = {AlignedAddr->getType()}; in emitMaskedAtomicRMWIntrinsic()
2844 {AlignedAddr, Incr, Mask, SextShamt, Ordering}); in emitMaskedAtomicRMWIntrinsic()
2847 Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering}); in emitMaskedAtomicRMWIntrinsic()
2865 IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, in emitMaskedAtomicCmpXchgIntrinsic() argument
2876 Type *Tys[] = {AlignedAddr->getType()}; in emitMaskedAtomicCmpXchgIntrinsic()
2880 MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering}); in emitMaskedAtomicCmpXchgIntrinsic()
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVISelLowering.h224 Value *AlignedAddr, Value *Incr,
231 Value *AlignedAddr, Value *CmpVal,
DRISCVISelLowering.cpp3524 IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, in emitMaskedAtomicRMWIntrinsic() argument
3529 Type *Tys[] = {AlignedAddr->getType()}; in emitMaskedAtomicRMWIntrinsic()
3555 {AlignedAddr, Incr, Mask, SextShamt, Ordering}); in emitMaskedAtomicRMWIntrinsic()
3558 Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering}); in emitMaskedAtomicRMWIntrinsic()
3576 IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, in emitMaskedAtomicCmpXchgIntrinsic() argument
3587 Type *Tys[] = {AlignedAddr->getType()}; in emitMaskedAtomicCmpXchgIntrinsic()
3591 MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering}); in emitMaskedAtomicCmpXchgIntrinsic()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DAtomicExpandPass.cpp615 Value *AlignedAddr; member
662 Ret.AlignedAddr = Builder.CreateIntToPtr( in createMaskInstrs()
767 insertRMWCmpXchgLoop(Builder, PMV.WordType, PMV.AlignedAddr, MemOpOrder, in expandPartwordAtomicRMW()
800 AtomicRMWInst *NewAI = Builder.CreateAtomicRMW(Op, PMV.AlignedAddr, in widenPartwordAtomicRMW()
879 LoadInst *InitLoaded = Builder.CreateLoad(PMV.WordType, PMV.AlignedAddr); in expandPartwordCmpXchg()
893 PMV.AlignedAddr, FullWord_Cmp, FullWord_NewVal, CI->getSuccessOrdering(), in expandPartwordCmpXchg()
966 Builder, AI, PMV.AlignedAddr, ValOperand_Shifted, PMV.Mask, PMV.ShiftAmt, in expandAtomicRMWToMaskedIntrinsic()
988 Builder, CI, PMV.AlignedAddr, CmpVal_Shifted, NewVal_Shifted, PMV.Mask, in expandAtomicCmpXchgToMaskedIntrinsic()
/external/llvm/lib/CodeGen/
DAtomicExpandPass.cpp567 Value *AlignedAddr; member
614 Ret.AlignedAddr = Builder.CreateIntToPtr( in createMaskInstrs()
719 insertRMWCmpXchgLoop(Builder, PMV.WordType, PMV.AlignedAddr, MemOpOrder, in expandPartwordAtomicRMW()
796 LoadInst *InitLoaded = Builder.CreateLoad(PMV.WordType, PMV.AlignedAddr); in expandPartwordCmpXchg()
810 PMV.AlignedAddr, FullWord_Cmp, FullWord_NewVal, CI->getSuccessOrdering(), in expandPartwordCmpXchg()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp1245 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); in emitAtomicBinaryPartword() local
1307 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) in emitAtomicBinaryPartword()
1346 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); in emitAtomicBinaryPartword()
1370 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); in emitAtomicBinaryPartword()
1500 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); in emitAtomicCmpSwapPartword() local
1570 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) in emitAtomicCmpSwapPartword()
1601 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); in emitAtomicCmpSwapPartword()
1618 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); in emitAtomicCmpSwapPartword()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsISelLowering.cpp1664 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); in emitAtomicBinaryPartword() local
1783 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) in emitAtomicBinaryPartword()
1810 .addReg(AlignedAddr) in emitAtomicBinaryPartword()
1913 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); in emitAtomicCmpSwapPartword() local
1970 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) in emitAtomicCmpSwapPartword()
2002 .addReg(AlignedAddr) in emitAtomicCmpSwapPartword()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsISelLowering.cpp1662 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); in emitAtomicBinaryPartword() local
1781 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) in emitAtomicBinaryPartword()
1808 .addReg(AlignedAddr) in emitAtomicBinaryPartword()
1911 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); in emitAtomicCmpSwapPartword() local
1968 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) in emitAtomicCmpSwapPartword()
2000 .addReg(AlignedAddr) in emitAtomicCmpSwapPartword()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetLowering.h1732 Value *AlignedAddr, Value *Incr, in emitMaskedAtomicRMWIntrinsic() argument
1742 IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, in emitMaskedAtomicCmpXchgIntrinsic() argument
/external/llvm-project/llvm/include/llvm/CodeGen/
DTargetLowering.h1869 Value *AlignedAddr, Value *Incr, in emitMaskedAtomicRMWIntrinsic() argument
1879 IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, in emitMaskedAtomicCmpXchgIntrinsic() argument
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp3233 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, in lowerATOMIC_LOAD_OP() local
3262 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, in lowerATOMIC_LOAD_OP()
3337 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, in lowerATOMIC_CMP_SWAP() local
3353 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift, in lowerATOMIC_CMP_SWAP()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp3852 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, in lowerATOMIC_LOAD_OP() local
3881 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, in lowerATOMIC_LOAD_OP()
3968 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, in lowerATOMIC_CMP_SWAP() local
3984 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift, in lowerATOMIC_CMP_SWAP()
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp3904 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, in lowerATOMIC_LOAD_OP() local
3933 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, in lowerATOMIC_LOAD_OP()
4020 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, in lowerATOMIC_CMP_SWAP() local
4036 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift, in lowerATOMIC_CMP_SWAP()