| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonLoopIdiomRecognition.cpp | 1634 Instruction *And1 = dyn_cast<Instruction>(I->getOperand(1)); in setupPreSimplifier() local
1635 if (!And0 || !And1) in setupPreSimplifier()
1638 And1->getOpcode() != Instruction::And) in setupPreSimplifier()
1640 if (And0->getOperand(1) != And1->getOperand(1)) in setupPreSimplifier()
1643 return B.CreateAnd(B.CreateXor(And0->getOperand(0), And1->getOperand(0)), in setupPreSimplifier()
1766 Instruction *And1 = dyn_cast<Instruction>(Xor->getOperand(1)); in setupPostSimplifier() local
1769 std::swap(And0, And1); in setupPostSimplifier()
1778 return B.CreateAnd(B.CreateXor(And0->getOperand(0), And1), C0); in setupPostSimplifier()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonLoopIdiomRecognition.cpp | 1615 Instruction *And1 = dyn_cast<Instruction>(I->getOperand(1)); in setupPreSimplifier() local
1616 if (!And0 || !And1) in setupPreSimplifier()
1619 And1->getOpcode() != Instruction::And) in setupPreSimplifier()
1621 if (And0->getOperand(1) != And1->getOperand(1)) in setupPreSimplifier()
1624 return B.CreateAnd(B.CreateXor(And0->getOperand(0), And1->getOperand(0)), in setupPreSimplifier()
1747 Instruction *And1 = dyn_cast<Instruction>(Xor->getOperand(1)); in setupPostSimplifier() local
1750 std::swap(And0, And1); in setupPostSimplifier()
1759 return B.CreateAnd(B.CreateXor(And0->getOperand(0), And1), C0); in setupPostSimplifier()
|
| /external/oboe/samples/RhythmGame/third_party/glm/gtx/ |
| D | simd_vec4.inl | 320 __m128 And1 = _mm_and_ps(Flr1, Cmp1); local
322 return _mm_or_ps(And0, And1);
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 875 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); in performORCombine() local
888 if (And1.getOpcode() == ISD::AND && in performORCombine()
889 And1.getOperand(0).getOpcode() == ISD::SHL) { in performORCombine()
891 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || in performORCombine()
899 SDValue Shl = And1.getOperand(0); in performORCombine()
926 bool isConstCase = And1.getOpcode() != ISD::AND; in performORCombine()
927 if (And1.getOpcode() == ISD::AND) { in performORCombine()
928 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) in performORCombine()
945 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); in performORCombine()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 876 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); in performORCombine() local
889 if (And1.getOpcode() == ISD::AND && in performORCombine()
890 And1.getOperand(0).getOpcode() == ISD::SHL) { in performORCombine()
892 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || in performORCombine()
900 SDValue Shl = And1.getOperand(0); in performORCombine()
927 bool isConstCase = And1.getOpcode() != ISD::AND; in performORCombine()
928 if (And1.getOpcode() == ISD::AND) { in performORCombine()
929 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) in performORCombine()
946 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); in performORCombine()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 4066 auto And1 = MIRBuilder.buildAnd(Src1Ty, Src0, SignBitMask); in lowerFCopySign() local
4067 Or = MIRBuilder.buildOr(Dst, And0, And1); in lowerFCopySign()
4072 auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask); in lowerFCopySign() local
4073 Or = MIRBuilder.buildOr(Dst, And0, And1); in lowerFCopySign()
4078 auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask); in lowerFCopySign() local
4079 Or = MIRBuilder.buildOr(Dst, And0, And1); in lowerFCopySign()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 2253 SDValue And1 = N->getOperand(1); in tryBitfieldInsertOpFromOr() local
2254 if (And0.hasOneUse() && And1.hasOneUse() && in tryBitfieldInsertOpFromOr()
2256 isOpcWithIntImmediate(And1.getNode(), ISD::AND, Mask1Imm) && in tryBitfieldInsertOpFromOr()
2264 std::swap(And0, And1); in tryBitfieldInsertOpFromOr()
2268 SDValue Src = And1->getOperand(0); in tryBitfieldInsertOpFromOr()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 2462 SDValue And1 = N->getOperand(1); in tryBitfieldInsertOpFromOr() local
2463 if (And0.hasOneUse() && And1.hasOneUse() && in tryBitfieldInsertOpFromOr()
2465 isOpcWithIntImmediate(And1.getNode(), ISD::AND, Mask1Imm) && in tryBitfieldInsertOpFromOr()
2473 std::swap(And0, And1); in tryBitfieldInsertOpFromOr()
2477 SDValue Src = And1->getOperand(0); in tryBitfieldInsertOpFromOr()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 2643 SDValue And1 = N->getOperand(1); in tryBitfieldInsertOpFromOr() local
2644 if (And0.hasOneUse() && And1.hasOneUse() && in tryBitfieldInsertOpFromOr()
2646 isOpcWithIntImmediate(And1.getNode(), ISD::AND, Mask1Imm) && in tryBitfieldInsertOpFromOr()
2654 std::swap(And0, And1); in tryBitfieldInsertOpFromOr()
2658 SDValue Src = And1->getOperand(0); in tryBitfieldInsertOpFromOr()
|
| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 5424 auto And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask); in lowerFCopySign() local
5425 Or = MIRBuilder.buildOr(Dst, And0, And1); in lowerFCopySign()
5430 auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask); in lowerFCopySign() local
5431 Or = MIRBuilder.buildOr(Dst, And0, And1); in lowerFCopySign()
5436 auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask); in lowerFCopySign() local
5437 Or = MIRBuilder.buildOr(Dst, And0, And1); in lowerFCopySign()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 734 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); in performORCombine() local
747 if (And1.getOpcode() != ISD::AND) in performORCombine()
750 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || in performORCombine()
758 SDValue Shl = And1.getOperand(0); in performORCombine()
|
| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineCompares.cpp | 4045 Value *And1 = Builder->CreateAnd(BO0->getOperand(0), Mask); in visitICmpInst() local
4047 return new ICmpInst(I.getPredicate(), And1, And2); in visitICmpInst()
|
| /external/llvm-project/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineCompares.cpp | 4080 Value *And1 = Builder.CreateAnd(BO0->getOperand(0), Mask); in foldICmpBinOp() local
4082 return new ICmpInst(Pred, And1, And2); in foldICmpBinOp()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineCompares.cpp | 4004 Value *And1 = Builder.CreateAnd(BO0->getOperand(0), Mask); in foldICmpBinOp() local
4006 return new ICmpInst(Pred, And1, And2); in foldICmpBinOp()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 6019 SDValue And1 = DAG.getNode(ISD::AND, DL, ShVT, NegOp1, BitWidthMinusOneC); in expandROT() local
6021 DAG.getNode(HsOpc, DL, VT, Op0, And1)); in expandROT()
|
| D | DAGCombiner.cpp | 5106 SDValue Not = And->getOperand(0), And1 = And->getOperand(1); in combineShiftAnd1ToBitTest() local
5109 if (!isBitwiseNot(Not) || !Not.hasOneUse() || !isOneConstant(And1)) in combineShiftAnd1ToBitTest()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 5391 SDValue Not = And->getOperand(0), And1 = And->getOperand(1); in combineShiftAnd1ToBitTest() local
5394 if (!isBitwiseNot(Not) || !Not.hasOneUse() || !isOneConstant(And1)) in combineShiftAnd1ToBitTest()
|